Schmitt trigger circuit

Details Schmitt trigger circuit Schmitt trigger circuit

1999-06-21

2002-01-01

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S215000, C327S225000

Reexamination Certificate

active

06335649

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit, in particular to a Schmitt trigger circuit having hysterisis characteristics in threshold level.
2. Description of Related Art
A signal transmitted long distance by such as bus line may contain substantial noise. In order to prevent an erroneous operation of a signal processing device due to such noise mixed in the signal, a Schmitt trigger circuit is frequently used.
The Schmitt trigger circuit has hysterisis characteristics in its threshold level.
FIG. 2
is a block circuit diagram showing an example of construction of a conventional Schmitt trigger circuit and
FIG. 3
is a circuit diagram showing an example of construction of an inverter used in the Schmitt trigger circuit shown in FIG.
2
.
In
FIG. 2
, the conventional Schmitt trigger circuit is constructed with a first and second inverters INV
1
and INV
2
each of which inverts an input signal Vin input to an input terminal
6
of the Schmitt trigger circuit at a predetermined threshold level as a boundary, a third inverter INV
3
which inverts an output signal of the second inverter INV
2
, an RS flip-flop
7
composed of two NAND gates NAND
1
and NAND
2
and a fourth inverter INV
4
which inverts an output signal of the RS flip-flop
7
and outputs the inverted signal as an output signal Vo through an output terminal
8
of the Schmitt trigger circuit.
Incidentally, a voltage (threshold voltage level) of the input signal Vin at which the output signal Vo is switched from an L (low) voltage level to a H (high) voltage level when the input signal Vin is changed in a direction from an L voltage level to a H voltage level is referred to as “positive trigger voltage”. A voltage (threshold voltage level) of the input signal Vin at which the output signal Vo is switched from the H voltage level to the L voltage level when the input signal Vin is changed in a direction from the H voltage level to the L voltage level is referred to as “negative trigger voltage”.
A threshold voltage level of the first inverter INV
1
is equal to the positive trigger voltage of the Schmitt trigger circuit, which is high compared with a threshold voltage level of the third inverter INV
3
or the fourth inverter INV
4
. A threshold voltage level of the second inverter INV
2
is equal to a negative trigger voltage of the Schmitt trigger circuit, which is low compared with the threshold level of the third inverter INV
3
or the fourth inverter INV
4
.
In
FIG. 3
, each of the first to fourth inverters INV
1
to INV
4
is composed of a P channel MOSFET
91
and an N channel MOSFET
92
which have drains D connected commonly and gates G connected commonly too. A source S of the P channel MOSFET
91
is connected to a power source V
DD
and a source S of the N channel MOSFET
92
is grounded. A signal is input to the gates G of the P channel MOSFET
91
and the N channel MOSFET
92
and an output signal obtained by inverting the input signal is output from the drains D thereof.
Incidentally, the threshold voltage levels of the first to fourth inverters INV
1
to INV
4
are determined by ratios of resistances of the P channel MOSFET's
91
and
92
thereof, respectively.
An operation of the Schmitt trigger circuit shown in
FIG. 2
will be described with reference to
FIG. 4
which shows a timing chart of the operation of the Schmitt trigger circuit.
In
FIG. 4
, when an input signal Vin having a waveform such as shown in FIG.
4
(
a
) is inputted to the input terminal
6
, the first inverter INV
1
outputs an inverted signal with a timing shown in FIG.
4
(
b
), since the threshold level of the first inverter INV
1
is set to the high level compared with the threshold level of the third inverter INV
3
or the fourth inverter INV
4
.
On the other hand, the second inverter INV
2
outputs the inverted signal with a timing shown in FIG.
4
(
c
), since the threshold level of the second inverter INV
2
is set to the low value.
An output of the RS flip-flop
7
is set to a L level when the input from the first inverter INV
1
is the L level and reset to a H level when the input from the third inverter INV
3
is in the L level. That is, as shown in FIG.
4
(
d
), the output of the RS flip-flop
7
is switched from the H level to the L level with the timing of the threshold level of the first inverter INV
1
when the input signal Vin is changed in a direction from the L level to the H level and switched from the L level to the H level with the timing of the threshold level of the second inverter INV
2
when the input signal Vin is changed in a direction from the H level to the L level. In this manner, the Schmitt trigger circuit can have the hysterisis characteristics.
Although the RS flip-flop
7
is constructed with the two NAND gates in
FIG. 2
, the RS flip-flop may be constructed with two NOR gates.
As mentioned above, since the threshold level of the inverter is determined by the ratio of resistances of the P channel MOSFET and the N channel MOSFET constituting the inverter, it is necessary to set a value of resistance of the N channel MOSFET large compared with that of the P channel MOSFET when the threshold level of the first inverter is set.
Therefore, when the threshold level of the first inverter is made high in the conventional Schmitt trigger circuit shown in
FIG. 2
, a drive performance of the N channel MOSFET of the inverter is lowered, so that a delay time of the Schmitt trigger circuit is increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a Schmitt trigger circuit capable of preventing a delay time from being increased.
In order to achieve the above object, the Schmitt trigger circuit having hysterisis characteristics in threshold level, according to the present invention, comprises a first inverter for setting a positive trigger voltage which is a threshold voltage level when an input signal is changed in a direction from a low voltage level to a high voltage level, a second inverter for setting a negative trigger voltage which is a threshold level when an input signal is changed in a direction from a high voltage level to a low voltage level, and a level shift circuit for shifting the input signal voltage level down by a constant voltage and supplying the voltage shifted input signal to the first inverter.
In the present Schmitt trigger circuit having the level shift circuit for lowering the input voltage by a predetermined constant voltage and supplying it to the first inverter, it is possible to set the positive trigger voltage to a similar value to that in the conventional Schmitt trigger circuit even when the threshold level of the first inverter is set to a value lower than the conventional value by the predetermined constant voltage.


REFERENCES:
patent: 4563594 (1986-01-01), Koyama
patent: 4603264 (1986-07-01), Nakano
patent: 4719367 (1988-01-01), Denda
patent: 4859873 (1989-08-01), O'Shaughnessy et al.
patent: 5036226 (1991-07-01), Tonnu et al.
patent: 5327020 (1994-07-01), Ikeda
patent: 401073912 (1987-09-01), None

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