Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-06-15
2001-01-30
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S212000
Reexamination Certificate
active
06181179
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a scan flip-flop circuit and, more particularly, to a scan flip-flop circuit used to perform a scan test for a semiconductor integrated circuit.
A scan test for detecting a fault of a semiconductor integrated circuit has used a scan flip-flop circuit, as disclosed in Japanese Patent Laid-Open No. 1-96573.
FIG. 5
shows a conventional scan flip-flop circuit.
In
FIG. 5
, the scan flip-flop circuit comprises a selector
40
on the input stage, a master latch
41
for receiving an output from the selector
40
, a slave latch
43
for receiving an output from the master latch
41
, and a clock unit
44
.
The selector
40
comprises a transmission gate
401
for enabling/disabling (on/off) an input signal D, and a transmission gate
402
for enabling/disabling an input signal SIN. The outputs of the transmission gates
401
and
402
are commonly connected to the subsequent master latch
41
. The selector
40
selects either one of the data input signal D input as a normal logic signal in normal operation and the scan input signal SIN input as a scan logic signal in a scan test.
The clock unit
44
generates a signal for controlling each transmission gate formed at the corresponding portion in the scan flip-flop circuit on the basis of a clock signal CLK and control signal SEL. In the clock unit
44
, the clock signal CLK is input to an inverter
441
to output the logically inverted signal as a clock signal AB. The clock signal AB is input to an inverter
442
to output the logically inverted signal as a clock signal A.
The control signal SEL is input to an inverter
443
to output the logically inverted signal as a control signal BB. The control signal BB is input to an inverter
444
to output the logically inverted signal as a control signal B.
In normal operation, the control signal SEL=0 (L level) is set to set the control signal BB=1 and the control signal B=0. Thus, the transmission gate
401
of the selector
40
is turned on to output the input signal D to the master latch
41
.
In a scan test, the control signal SEL=1 (H level) is set to set the control signal BB=0 and the control signal B=1. Thus, the transmission gate
402
of the selector
40
is turned on to output the input signal SIN to the master latch
41
.
The master latch
41
comprises a transmission gate
411
for enabling/disabling an output from the selector
40
, and an inverter
412
for inverting and outputting an output from the transmission gate
411
. An inverter
413
for inverting and outputting an output from the inverter
412
, and a transmission gate
414
for connecting/disconnecting the output of the inverter
413
to/from the input of the inverter
412
are series-connected between the input and output of the inverter
412
.
The inverters
412
and
413
and transmission gate
414
constitute a latch. An output from the inverter
412
is output to the subsequent slave latch
43
via a transmission gate
415
.
The slave latch
43
comprises an inverter
431
for inverting and outputting an output from the master latch
41
, an inverter
432
for inverting and outputting an output from the inverter
431
, and a transmission gate
433
for connecting/disconnecting the output of the inverter
432
to/from the input of the inverter
431
. The inverters
431
and
432
and transmission gate
433
constitute a latch, and an output from the slave latch
43
is output as an output signal Q.
Operation in a scan test will be explained with reference to
FIGS. 6A
to
6
I.
In a scan test, the control signal SEL=0 (
FIG. 6B
) is set to turn on the transmission gate
402
(FIG.
6
C). In this state, for a clock signal CLK=0, e.g., before time T
1
(FIG.
6
A), the clock signal AB=1 and the clock signal A=0 hold. In the master latch
41
, the transmission gate
411
is turned on (
FIG. 6D
) to input the scan logic input signal SIN (
FIG. 6H
) from the selector
40
to the inverter
412
.
At time T
1
, the clock signal CLK=1 is set to set the clock signal AB=0 and the clock signal A=1. Thus, the transmission gate
411
is turned off, and the transmission gate
414
is turned on (
FIGS. 6D and 6E
) to latch an output from the inverter
412
.
At this time, the transmission gate
415
is also turned on (
FIG. 6F
) to input an output from the inverter
412
to the slave latch
43
. Then, the inverter
431
outputs the inverted output as the output signal Q (FIG.
6
I). At time T
2
, the clock signal CLK=0 is set to latch the output signal Q by the slave latch
43
(FIG.
6
G).
The conventional scan flip-flop circuit comprises the selector
40
for selecting either one of the normal logic input signal D and scan logic input signal SIN by the external control signal SEL depending on normal operation or scan test. Even in normal operation, this selector
40
exists on the path of the normal logic input signal D to delay propagation of the input signal D, failing to operate the scan flip-flop circuit at a higher speed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a scan flip-flop circuit having higher-speed operation characteristics in normal operation.
To achieve the above object, according to the present invention, there is provided a scan flip-flop circuit comprising a first master latch for latching a data input signal and outputting the data input signal to a first output terminal in a normal operation mode, a second master latch for latching a scan input signal and outputting the scan input signal to a second output terminal in a scan test mode, a slave latch for latching an output from the first master latch that is input to a first input terminal, thereby outputting the output to a third output terminal in the normal operation mode, and latching an output from the second master latch that is input to a second input terminal, thereby outputting the output to the third output terminal in the scan test mode, first switch means for disconnecting the first output terminal of the first master latch from the first input terminal of the slave latch in the scan test mode, second switch means for disconnecting the first output terminal of the second master latch from the second input terminal of the slave latch in the normal operation mode, and third switch means which is connected between the first and second input terminals of the slave latch, connects the second output terminal of the second master latch to the first input terminal via the second input terminal of the slave latch upon ON operation in the scan test mode, and disconnects the second output terminal of the second master latch from the first input terminal of the slave latch upon OFF operation in the normal operation mode.
REFERENCES:
patent: 5257223 (1993-10-01), Dervisoglu
patent: 5469079 (1995-11-01), Mahant-Shetti et al.
patent: 5689517 (1997-11-01), Ruparel
patent: 6006348 (1999-12-01), Sode et al.
patent: 1-96573 (1989-04-01), None
patent: 2-205109 (1990-08-01), None
patent: 8-5710 (1996-01-01), None
patent: 9-43314 (1997-02-01), None
patent: 9-270677 (1997-10-01), None
McGuireWoods LLP
NEC Corporation
Tran Toan
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