Scan circuit having a reduced clock signal delay

Details Scan circuit having a reduced clock signal delay Scan circuit having a reduced clock signal delay

1995-02-28

1997-08-05

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327295, 327288, 327161, 327250, 377 79, H03K 514, H03K 3356

Patent

active

056546599

ABSTRACT:
A scan circuit includes a plurality of stages of cascaded pulse delay transfer circuits each including a single-phase-clock controlled inverter connected in cascade and configured to receive a given pulse signal from a preceding stage so as to transfer the received pulse signal to a next stage at a delayed timing in synchronism with a clock signal, and a two-input logic gate having a first input connected to an output of the associated single-phase-clock controlled inverter and a second input receiving the same clock signal. The two-input logic gate of an odd-numbered stage includes a NOR gate, which has an output connected to a non-inverting output buffer. The two-input logic gate of an even-numbered stage includes a NAND gate, which has an output connected to an inverting output buffer.

REFERENCES:
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patent: 4443765 (1984-04-01), Findeisen et al.
patent: 4694197 (1987-09-01), Sprague
patent: 4794276 (1988-12-01), Sasada et al.
patent: 5220216 (1993-06-01), Woo
patent: 5239206 (1993-08-01), Yanai
patent: 5463337 (1995-10-01), Leonowich
Kindaikagakusha, "Fundamental of MOS INtegrate Circuit", Japan, pp. 101-102, 1992. No month.
Yuan, et al., "High-Speed CMOS Circuit Technique", IEEE Journal of Solid State Citcuits, V24 N1, Feb. 1989, pp. 62-70.

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