Scan flip-flop circuit capable of guaranteeing normal operation

Details Scan flip-flop circuit capable of guaranteeing normal operation Scan flip-flop circuit capable of guaranteeing normal operation

2005-03-29

2005-03-29

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C714S726000

Reexamination Certificate

active

06873197

ABSTRACT:
In a scan flip-flop circuit, a first master latch circuit receives usual mode data at a usual data input terminal in synchronization with a first clock signal. A second master latch circuit receives scan-in data at a scan-in data input terminal in synchronization with first and second scan clock signals. A slave latch circuit receives an output signal of the first master latch circuit in synchronization with said first clock signal and the second scan clock signal. The slave latch circuit is constructed by a control circuit for controlling transfer of the usual mode data to the output terminal in synchronization with the second scan clock signal.

REFERENCES:
patent: 5689517 (1997-11-01), Ruparel
patent: 6181179 (2001-01-01), Kanba
patent: 6240536 (2001-05-01), Mikan et al.
patent: 01-096573 (1989-04-01), None
patent: 2000-002754 (2000-01-01), None

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