Scan flip-flop that holds state during shifting

Details Scan flip-flop that holds state during shifting Scan flip-flop that holds state during shifting

1995-07-20

1997-05-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327203, 327208, 327210, 327211, H03K 3289

Patent

active

056336063

ABSTRACT:
A scan flip-fop is designed to hold the state of the slave latch during scan shifting. This allows an ATPG tool to develop robust delay path tests using combinational scan flip-flop models. Combinational scan flip-flop models suffice because the launch can be done in the cycle before test enable goes active and capture can be performed during the cycle in which test enable is active. Thus, multiple clocks during the capture cycle are not necessary and, therefore, sequential delay path ATPG is not necessary. It is only necessary for the ATPG tool to store the last parallel vector in a buffer. The dynamic latch used for the scan slave latch is made small and slow, thereby increasing the delay along the data path during shifting, making the cell immune to hold time violation for any reasonable amount of clock skew.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 5015875 (1991-05-01), Giles et al.
patent: 5175447 (1992-12-01), Kawasaki et al.
patent: 5444404 (1995-08-01), Ebzery
patent: 5463338 (1995-10-01), Yurash

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