Scheme for reducing leakage current in an input buffer

Details Scheme for reducing leakage current in an input buffer Scheme for reducing leakage current in an input buffer

1998-12-28

2001-11-27

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S322000, C327S530000, C326S027000, C326S083000, C307S412000

Reexamination Certificate

active

06323701

ABSTRACT:

FIELD OF INVENTION
The present application relates to the field of electronic circuitry. In particular the present application discloses apparatus and methods for addressing leakage in CMOS environments.
BACKGROUND OF THE INVENTION
A problem associated with leakage is shown in FIG.
1
.
FIG. 1
shows a typical CMOS inverter circuit
100
. CMOS logic circuits are specified to be compatible not only for CMOS level (0 to 3.3 v) input signals but also TTL level (0.4 to 2.4 v) input signals. The TTL requirement typically causes leakage in PFET
101
a
. Specifically, if input node
103
a
has a TTL level logic high (V
IH
) input of 2.4 volts, the gate to source voltage of PFET
101
a
is 0.9 volts for a 3.3 volt supply node
105
a
. Such a voltage causes PFET
101
a
to turn “on”.
However, since this is an inverting circuit, a logic high input ideally turns PFET
101
a
“off” and NFET
102
a
“on” resulting in ground voltage at output node
104
a
and no current flow from supply node
105
a
through PFET
101
a.
If the TTL high input turns PFET
101
a
“on”, leakage current flows from supply node
105
a
through PFET
101
a
(and most likely through NFET
102
a
to round). Obviously, an integrated circuit having potentially tens or hundreds of inverting or similar circuits will dramatically increase its power consumption if the leakage just described occurs. Thus, some form of addressing the leakage is necessary.
Some solutions for addressing this leakage problem boost the input voltage after its supplied at input node
103
a
such that the voltage at the gate of PFET 101
a
is high enough to cut off PFET
101
a
. However, this solution is not permissible with specifications requiring high input resistance. Thus the solution is not practicable in relation to most all industry requirements.
FIG. 2
shows a more robust design for addressing the leakage problem just described. Three stages are shown in circuit
200
of FIG.
2
: a buffer stage
201
a
, a variable supply stage
202
a
, and a logical detect stage
204
. As shown, the buffer stage supply node
210
a
is coupled to the variable supply stage output
211
a
at net
203
; the buffer stage output
212
a
is coupled to the output node
104
b
and the logic detect stage input
213
a
at net
209
; the logic detect stage output
214
a
is coupled to the variable supply stage input
215
a
at net
205
and the variable supply stage supply node
216
a
is coupled to supply node
105
b
. Input node
103
b
is coupled to buffer stage input
218
a.
The buffer stage
201
a
is simply the inverter circuit
100
of FIG.
1
. However, “buffer stages” may be almost any conceivable design having leakage. Variable supply stage
202
a
modulates the voltage or current applied to buffer stage supply node
210
a
in such a manner that voltage and/or current is limited when the logic detect stage
204
senses a logic low at output node
104
b
. A logic low at output node
104
b
means leakage is possible as input node
103
b
must be high. Thus the logic detect stage cuts off the power to buffer stage
201
a
if leakage is possible. Buffer stage supply node
210
a
reverts back to the supply voltage (i.e. voltage at supply node
105
b
) when the logic detect stage
204
senses a logic high. That is, the supply voltage returns when leakage is impossible (input node
103
b
is low).
Thus, the logical detect stage
204
merely detects the logic level at buffer stage output
212
a.
In the example of circuit
200
, variable supply stage
202
a
has a switch transistor
207
and a decoupling capacitor
208
. Ideally, when there is no possibility of leakage (i.e., when input node
103
b
is low), switch transistor
207
is on and the full supply voltage appears at the buffer stage supply node
210
a
. When leakage is possible (i.e., when input node
103
b
is high), switch transistor
207
is off leaving the decoupling capacitor
208
as the sole voltage source at the source of PFET
101
b
. The decoupling capacitor
208
voltage is then a function of the amount of leakage through PFET
101
b
, if any exists.
Problems exist, however, if one employs a logic detect stage
204
. One problem is that the voltage at buffer stage supply node
210
a
is cut off from supply node
105
b
even if no actual leakage exists. The voltage is cut off if leakage is merely possible. That is, if a CMOS level high signal (approx. 3.3) is placed at input node
103
b
the switch transistor
207
is cut off even though there is no risk of leakage through transistor
101
b
. Anytime the voltage at buffer stage supply node
210
a
is dropped, a corresponding reduction in circuit speed is realized. That is, at output node
104
b
there is typically some capacitive loading
217
. Anytime the voltage at buffer stage
201
a
supply node
210
a
is reduced, the charge/discharge time at output node
104
b
lengthens. Thus use of a logic detect stage
204
results in slower circuit speed not only for TTL level but also CMOS level input signals at input node
103
b.
A further problem involves decoupling capacitor
208
as shown and described with reference to FIG.
3
.
FIGS. 3
a-
3
c
show critical voltages for cases where the high to low transition of the input voltage at input node
103
b
is ideal.
FIGS. 3
d-
3
f
show the same critical voltages if the input voltage transition is less than ideal. Use of circuit
200
of
FIG. 2
results in improper circuit operation for the input voltage shown in
FIG. 3
d
. Essentially circuit
200
only works for synchronous applications and not asynchronous applications.
“Synchronous” simply means some kind of clocking or other mechanism exists whereby critical voltages must make logic transitions (either high to low or low to high) within some limited time period. “Asynchronous” environments have no such limited time period. Therefore, it is possible for practically unlimited transition time periods (such as that shown in
FIG. 3
d
) within asynchronous environments but not in synchronous environments (i.e., the transition shown in
FIG. 3
a
is almost necessary in synchronous environments).
FIG. 3
a
is a schematic depiction of an ideal TTL input voltage signal. The fall time from the voltage high level (V
IH
=2.4 volts) to the logic low level (V
IL
=0.4 volts) is zero. Better put, the transition from logic high to logic low is instantaneous. For instantaneous transitions the source voltage of PFET transistor
101
b
and the output node
104
b
voltage are shown in
FIGS. 3
b
and
3
c
respectively.
As shown in
FIG. 3
b
, while the input node
103
b
voltage is at a TTL level logic high (V
IH
=2.4 v), the source voltage of PFET
101
b
slightly less than V
IH
+V
T
(=2.4+0.7=3.1). This voltage results from the fact that, as discussed, switch transistor
207
is cut off by logic detect stage
204
when logic level high signals are placed input node
103
b
. At the time switch transistor
207
is cut off, which is shortly after the input voltage transitions from low to high (not shown in
FIG. 3
a
or
3
d
), the voltage at decoupling capacitor
208
(and the source of PFET
101
b
) is the full supply voltage at node
105
b
. This causes PFET
101
b
to leak. The source of leakage current is decoupling capacitor
208
since transistor
207
is cut off. As PFET
101
b
continues to leak, charge is continually drawn from decoupling capacitor
208
resulting in a continual voltage drop in decoupling capacitor
208
voltage and continued drop at the source of PFET
101
b
. This gradual decay in decoupling capacitor
208
voltage stops at the point where PFET
101
b
becomes cut off (i.e., when slightly less than the threshold voltage (V
T
) appears across the gate-to-source region of PFET
101
b
.) The source of PFET
101
b
is then “stuck” at slightly less than V
IH
+V
T
as no current path to ground exists from decoupling capacitor
208
. This is the state shown in
FIG. 3
b
prior to the high to low transition at t
oa
.
Once there is a transition at input node
103
b
from logic high to l

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