Scan flip-flop with power saving feature

Details Scan flip-flop with power saving feature Scan flip-flop with power saving feature

1994-03-03

1995-08-22

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327202, 326 16, 371 221, H03K 302

Patent

active

054444047

ABSTRACT:
A flip-flop has both a system output and a scan output. A system output signal for the flip-flop is placed on the system output. When the flip-flop is in a normal operating mode, a scan output signal on the scan output is held at a static logic level. When the flip-flop is in a scan mode, the scan output signal on the scan output transitions between logic 1 and logic 0 synchronous with transitions of the system output signal on the system output.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 5175447 (1992-12-01), Kawasaki et al.

Affiliated with

Also associated with

Rating

Scan flip-flop with power saving feature does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scan flip-flop with power saving feature, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan flip-flop with power saving feature will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2144730