Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-10-27
2002-04-16
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S219000, C327S215000, C327S225000, C327S218000
Reexamination Certificate
active
06373310
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electronic circuits, and in particular, to set/reset circuits.
2. Description of the Related Art
A conventional set/reset circuit
100
is shown in
FIG. 1
, formed by using a pair of cross-coupled NAND gates
102
,
104
. Alternatively, a pair of cross-coupled NOR gates could have been used. While the circuit
100
may be adequate for supporting a single pair of set and reset input terminals
106
,
108
, extending this configuration for multiple input pairs would be undesirable. Adding inputs to the circuit
100
would require either stacking transistors in series or using cascaded logic gates, both of which degrade timing performance.
FIG. 2
depicts a schematic diagram of a scalable set/reset circuit
200
formed with cross-coupled inverters
210
to hold the logical state at nodes NSET and NRESET when none of set signal (S
0
, S
1
, S
2
) or reset signal (R
0
, R
1
, R
2
) is asserted. The scalable set/reset circuit
200
includes one set of pull-down transistors
206
coupled to NSET and another set of pull-down transistors
208
coupled to NRESET. Each of the pull-down transistors Q
1
through Q
6
is stronger than the cross-coupled inverters
210
and is able to overcome the relatively weak inverters
202
,
204
to pull a corresponding node (NSET or NRESET) to logical low state.
FIG. 3
depicts a timing diagram for the scalable set/reset circuit
200
shown in
FIG. 2
, illustrating set and reset operations of the circuit. The output Q of the circuit is initially in a logical low state and the other output Q# is initially in a logical high state. At time T
1
, a set signal S
0
goes high, this low-to-high transition signal asserted to the gate of transistor Q
1
turns on the transistor Q
1
and pulls the node NSET low at time T
2
and the output signal Q high at time T
3
. The logic low at the node NSET provides logic high at the node NRESET, through inverter
202
, at time T
4
. When NRESET goes high, this causes output Q# to go from high to low at time T
5
. From time T
5
to T
6
, when neither the set nor reset signal is asserted, the cross-coupled inverters
210
function to hold the state of NSET and NRESET until a reset signal is applied. At T
6
, a reset signal R
0
is applied to the gate of transistor Q
2
which causes the transistor Q
2
to pull NRESET low at T
7
and the output Q# high at time T
8
. When the logical state of NRESET go from high to low, the inverter
204
will charge the node NSET to high.
While the set/reset circuit
200
of
FIG. 2
has an advantage over the circuit
100
of
FIG. 1
in that adding a pair of set and reset input terminals only requires the addition of a single pair of transistors to the node NSET and NRESET, one problem associated with the circuit shown in
FIG. 2
is that the rise and fall times of the outputs Q and Q# are asymmetric. The rise and fall times of the outputs Q and Q# are inherently mismatched because the cross-coupled inverters
210
are made weaker than the pull-down transistors Q
1
-Q
6
to enable the transistors to overcome the cross-coupled inverters to pull the corresponding node to logical low state. When setting the circuit
200
, NSET is pulled low relatively quickly by means of one of the pull-down transistors Q
1
, Q
3
, Q
5
coupled to NSET. Thus, the low-to-high transition of output Q, in response to a set signal asserted to the gate of one of the pull-down transistors, is relatively quick. When resetting the circuit
200
, the node NRESET is pulled low via one of the pull-down transistors Q
2
, Q
4
, Q
6
. This high-to-low transition of NRESET drives the node NSET high through the inverter
202
. Because the inverter
202
is a slower device than the pull-down transistors Q
2
, Q
4
or Q
6
, it will take a while longer to charge the node NSET to high. In this regard, NSET is pulled low much faster than it can be pulled high. This results in the fall time of output Q being greater than the rise time of output Q. This mismatch in rise and fall time of the output can cause problems in applications requiring relatively symmetric rise and fall times of output.
REFERENCES:
patent: 4980577 (1990-12-01), Baxter
patent: 5124568 (1992-06-01), Chen et al.
patent: 5241225 (1993-08-01), Okajima et al.
patent: 5528181 (1996-06-01), Suggs
patent: 5793236 (1998-08-01), Kosco
patent: 6011421 (2000-01-01), Jung
patent: 6147514 (2000-11-01), Shiratake
patent: 6232810 (2001-05-01), Oklobdzija et al.
Cunningham Terry D.
Nguyen Long
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