Scheme to improve performance of timing recovery systems for...

Details Scheme to improve performance of timing recovery systems for... Scheme to improve performance of timing recovery systems for...

2005-02-15

2005-02-15

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S003000, C360S053000

Reexamination Certificate

active

06856183

ABSTRACT:
A digital phase lock loop circuit including an error generation circuit for generating at least three error signals and a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals. By using at least three error signals, as opposed to just one, the drift in the sampling phase of the recovered clock is easily detected and corrected to reduce burst errors and to improve loss of lock (LOL) performance.

REFERENCES:
patent: 5521948 (1996-05-01), Takeuchi
patent: 5986830 (1999-11-01), Hein
patent: 5987562 (1999-11-01), Glover
patent: 6023383 (2000-02-01), Glover et al.
patent: 6111712 (2000-08-01), Vishakhadatta et al.
patent: 6208478 (2001-03-01), Chiu et al.
patent: 6308298 (2001-10-01), Blatchley et al.
Aziz, Pervez M.et al., Symbol Rate Timing Recovery for Higher Order Partial Response Channels, IEEE Journal on Selected Areas in Communications, vol. 9, No. 4, Apr. 2001, pp. 635-648.

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