Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-05-24
2002-05-14
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S206000, C327S215000
Reexamination Certificate
active
06388487
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Schmitt circuit that is used as an input circuit of a CMOS semiconductor IC device.
2. Description of the Prior Art
FIG. 12
illustrates in block form a conventional Schmitt circuit. Reference numeral
1
denotes generally a CMOS semiconductor IC device;
12
denotes a Schmitt circuit provided therein;
3
denotes an input side inverter which inverts a signal from an input node
6
and outputs it to an intermediate a node
7
;
4
denotes an output side inverter which inverts the signal from the intermediate node
7
and outputs it to an output node
8
; and
5
denotes feedback inverter which inverts the signal from the output node
8
and outputs it to the intermediate node
7
.
In the input side inverter
3
, reference numeral
3
a
denotes a power supply VCC;
3
b
denotes a P-channel MOS transistor (hereinafter referred to as a PMOS transistor);
3
c
denotes an N-channel MOS transistor (hereinafter referred to as an NMOS transistor); and
3
d
denotes a low, ground-level power supply VSS. In the output side inverter
4
, reference numeral
4
a
denotes a PMOS transistor; and
4
b
an NMOS transistor. In the feedback inverter
5
, reference numeral
5
a
denotes a PMOS transistor; and
5
b
denotes an NMOS transistor.
FIG. 2
is a table showing characteristics of a Schmitt circuit according to Embodiment 1 of the present invention and the conventional Schmitt circuit. As shown in the table, the Schmitt circuit
12
has, for its input signal, an H-side threshold value V
IH
and a smaller L-side threshold value V
IL
, and the difference between these threshold values is called a hysteresis width.
In the case where the input signal changes from the “H” to “L” level, the Schmitt circuit
12
yields an H (high-level) output at the time the input signal exceeds the threshold value V
IH
, whereas when the input signal changes from the “L” to “H” level, the Schmitt circuit
12
yields an L (low-level) output at the time the input signal goes below the threshold value V
IL
. Consequently, even if the waveform of the input signal is distorted, the Schmitt circuit is capable of providing the output signal without being affected by the distortion as long as the amplitude of the distortion is within the hysteresis width.
Now, the operation of the conventional Schmitt circuit
12
will be described. The input side inverter
3
is formed by the PMOS and NMOS transistors
3
b
and
3
c
of high driving power; the inverter
3
inverts the signal from the input node
6
and outputs the inverted signal to the intermediate node
7
with high intensity. The output side inverter
4
inverts the signal from the intermediate node
7
and outputs the inverted signal to the output node
8
. The feedback inverter
5
is formed by the PMOS and NMOS transistors
5
a
and
5
b
of low driving power as compared with the transistors
3
b
and
3
b;
the inverter
5
inverts the signal from the output node
8
and outputs the inverted signal to the intermediate node
7
with low intensity.
As a result, when the signal at the input node
6
is low-level, the signal to the intermediate node
7
goes high and the signal to the output node
8
low. When the signal at the input node
6
is high-level, the signal to the intermediate node
7
goes low and the signal to the output node
8
high.
In the case where the signal level at the input node
6
gradually changes from “L” to “H” level and is going to exceed the threshold value of the input side inverter
3
, it inverts the low-level signal from the input node
6
and outputs the inverted high-level signal to the intermediate node
7
, but the output intensity (hereinafter referred to simply as intensity) gradually decreases. When the input signal level has just exceeded the threshold value, the inverter
3
outputs a low-level signal with low intensity and then the output intensity gradually increases. On the other hand, since the output side inverter
4
has inverted the high-level signal from the intermediate node
7
and is outputting the inverted low-level signal to the output node
8
at the time the input side inverter
3
is providing the low-level signal to the output node
8
, the feedback inverter
5
inverts the low-level signal from the output node
8
and applies the inverted high-level signal to the intermediate node
8
with low intensity.
Accordingly, the input side inverter
3
outputs a high-level signal to the intermediate node
7
with low intensity first and then provides thereto a low-level signal with low intensity at first when the input signal level has just exceeded the threshold value. As long as the output side inverter
4
outputs a low-level signal, the feedback inverter
8
applies a high-level signal to the intermediate node
7
with low intensity; hence, the signal level at the intermediate node
7
does not go low immediately even if the input signal level at the input node
6
exceeds the threshold value of the input side inverter
3
. Thereafter, even if the feedback inverter
5
still continues to output the high-level signal to the intermediate node
7
with low intensity, the output side inverter
4
inverts the low-level signal from the intermediate node
7
and outputs the inverted high-level signal to the output node
8
at the time the signal level at the intermediate node
7
is made low by a high-intensity low-level output from the input side inverter
3
, and the feedback inverter
5
inverts the high-level signal from the output node
8
and applies the inverted high-level signal to the intermediate node
7
. Thus, the Schmitt circuit operates stably.
Since the conventional Schmitt circuit has such a construction as described above, the hysteresis width does not becomes no narrow even if the voltage of the power supply VCC
3
a
falls low due to performance variations of transistors. In some cases, the hysteresis width becomes rather wide.
In
FIG. 2
there are shown measured values of the hysteresis width of the conventional Schmitt circuit. With the power supply voltage set at 5 V, the threshold values V
IH
and V
IL
are 2.89 V and 2.15 V, respectively, and the hysteresis width, is 0.74 V; when the power supply voltage is 2 V, the threshold values V
IH
and V
IL
are 1.31 V and 0.51 V, respectively and the hysteresis width is. 0.80 V. That is, the hysteresis width does not vary with the rte of change of power supply voltage as desired.
In this instance, the lower the power supply voltage, the higher the rate of the hysteresis width to the power supply voltage and the narrower the widths between a predetermined high level of the input signal and the threshold value V
IH
and between a predetermined low level of the input signal and the threshold value V
IL
—this imposes difficulty on the signal providing side in satisfying such conditions.
For the same reasons, when the power supply voltage is low, a dull input signal causes a delay in the output.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a Schmitt circuit which permits reduction of the hysteresis width.
According to an aspect of the present invention, there is provided a Schmitt circuit which includes a feedback inverter which limits the intensity of its output signal to the intermediate node in accordance with a signal from the input node.
According to another aspect of the present invention, there is provided a Schmitt circuit which includes a NOR circuit which outputs the NOR of a control signal and a signal from the input node and a feedback inverter which limits the intensity of its output signal to the intermediate node in accordance with the signal from the input node.
According to another aspect of the present invention, there is provided a Schmitt circuit which includes a NAND circuit which outputs the NAND of a control signal and a signal from the input node and a feedback inverter which limits the intensity of its output signal to the intermediate node in accordance with the signal from the input node.
According t
Cunningham Terry D.
Dinh Paul
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