Physical block address recovery apparatus system and method...

Physical coding sublayer for a multi-pair gigabit transceiver

Physical coding sublayer for a multi-pair gigabit transceiver

Physical incremental backup using snapshots

Physical incremental backup using snapshots

Physical layer loop back method and apparatus

Physical layer loop back method and apparatus

Physical packaging position information processing system

PICA system timing measurement and calibration

Piggybacking of ECC corrections behind loads

Pin coupler for an integrated circuit tester

Pipeline architecture for maximum a posteriori (MAP) decoders

Pipeline architecture for maximum a posteriori (MAP) decoders

Pipeline circuit with a test circuit with small circuit scale an

Pipeline of additional storage elements to shift...

Pipeline testing method, pipeline testing system, pipeline...

Pipelined add-compare-select circuits and methods, and...

Pipelined architecture implementing recursion processes for...

Pipelined architecture to decode parallel and serial...

Pipelined Berlekamp-Massey error locator polynomial generating a