Pipeline testing method, pipeline testing system, pipeline...

Details Pipeline testing method, pipeline testing system, pipeline... Pipeline testing method, pipeline testing system, pipeline...

2000-11-30

2004-05-04

Iqbal, Nadeem (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S016000, C714S035000, C714S032000, C703S022000

Reexamination Certificate

active

06732297

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a testing method, test system, test instruction generation method and storage medium for an information processing device (processor) having a pipeline mechanism, and more particularly to a testing method, test system, test instruction generation method and storage medium that automatically generate leading instructions and subsequent instructions that interfere with resources.
2. Description of the Related Art
In recent years, information processing devices, and particularly, processors, have been making rapid advances. Processors with a fast processing speed generally use a pipeline mechanism. In the pipeline mechanism, basically instruction processing is divided into processing units that can be executed with the same number of clocks. Also, it is possible to increase the speed by overlapping execution of continuous instructions, and performing parallel processing.
However, when interaction with hardware resources occurs during a leading/subsequent instruction in a pipeline, the execution of the instruction with an ideal clock cycle is obstructed. In that case, it is necessary for the pipeline mechanism to perform exceptional hardware operation such as temporarily stopping processing in the pipeline. The pipeline mechanism is designed such that this kind of exceptional hardware operation can be performed by the pipeline mechanism. However, many design problems of a pipeline mechanism occur because operations such as mentioned above often occur at start up, so it is necessary to test the pipeline in order to verify the aforementioned operation.
FIG. 21
is a block diagram of a prior pipeline testing system.
FIG. 22
is a drawing explaining the test instructions and pipeline interlocks. The prior pipeline testing system will be explained using FIG.
21
. First, a pseudo random number is generated by a random-number generating process
90
. From this pseudo random number, a random instruction generation process
91
generates a random instruction string
92
. This generated instruction string is executed by the pipeline run mechanism (pipeline processor)
93
, and the results, which are the contents of the memory
97
and register
98
, are dumped in a dump area
95
.
On the other hand, the same generated instruction string is executed by a serial run mechanism or simulator
94
, and similarly, the results, which are the contents of the memory
97
and register
98
, are dumped to a dump area
96
. In other words, the test results are obtained by the simulator or the serial run mode when there is a serial run mode in the hardware, and the pipeline mechanism is verified by comparing those results with the pipeline execution results.
In addition, the pipeline is verified by matching the execution results when the instruction string is serially executed and when it is executed by the pipeline under any conditions.
In other words, when the results do not match, it is possible to verify that there is something abnormal with the pipeline mechanism. In this test, it is necessary to verify the operation when there is interference with resources. In
FIG. 22
, the execution stage for each pipeline is shown with ‘IF’ being instruction fetch, ‘D’ is instruction decode, ‘Reg’ is register reference, ‘E’ is operation, ‘MEM’ is memory access, and ‘W’ is write. The execution status of the pipeline when executing each instruction string in this case is shown in FIG.
22
.
In this example, between the second instruction (ADD) and the third instruction (SUB), a state of interference (register hazard) occurs with the resource GR
4
(register), and the third instruction is interlocked by the pipeline mechanism. In order to verify that an interlock such as this is performed properly, it is necessary to generate a test instruction string for causing resource interference to occur.
In a conventional test method, random instruction code was entered to the pipeline to cause a situation, where at certain timing, interaction with a hardware resource occurred by chance, or execution of the instruction string repeated that caused the interaction with the resource by chance. And the pipeline was verified by using its accident and design of the pipeline was improved from the verification results.
In this method, a pseudo random number was used to cause interaction with a hardware resource by chance, and by repeatedly entering an instruction string to the pipeline that often caused resource interaction to occur, design errors in the interlock mechanism of the pipeline were detected, and verification was performed expecting that after a set amount of time, quality of the interlock mechanism could be assured.
However, in this method, verification is not enough in the case that interlocks occur at timing in all stages of the pipeline. In other words, since the state of the pipeline is not considered at all, it is not possible to gain an understanding of which stage in the pipeline the interlock occurred, or what the leading/subsequent instruction at that time was. Therefore, important test items are lost, and there are no indicators for correctly evaluating the design quality. Also, since the instruction string employs randomness, redundancy is common and thus making the method inefficient.
In order to prevent these problems, there is one proposed idea to automatically generate a test instruction string to cause the interaction of the resource (for example, Japanese Laid Open Patent 7-73037). In this proposal, times to occupy the hardware resource of each instruction are inputted as a specification data, the test instruction is created by listing the competed status between a plurality of instructions and linking the instructions which have the completed status.
In verification of the interlock mechanism of the pipeline, it is important to perform a comprehensive test to learn the interlock conditions at each stage of the pipeline, and what instructions are in the pipeline when an interlock occurs. However, in the prior method there are the following problems.
(1) It is necessary to enter the specifications, however in the design verification step when specifications are changed frequently, it is necessary to enter the specifications each time, and this takes time.
(2) When there are mistakes or errors in the specifications, the instruction string will be totally meaningless. For example, due to recent high-speed processing, the time required for one stage in the pipeline is on the order of nano seconds, so it is very difficult to enter that small of an interval and generate the required instruction string.
(3) As described above, in order to generate an instruction string for comprehensively verifying the interlocks at each stage of the pipeline, it is necessary to enter many conditions, and realistically this is very difficult.
(4) With a simple CPU (processor), it is possible to enter the specifications with the prior manual procedure, and to generate a test instruction string, however with recent CPUs, there are hundreds of kinds of instructions and even just one instruction is a parallel instruction as is VLIW. Therefore, it is nearly impossible to manually enter all of the interference patterns.
SUMMARY OF THE INVENTION
The objective of this invention is to provide a pipeline testing method, pipeline test system, pipeline test instruction string generation method and storage medium for automatically setting interference conditions, and selecting two objective instructions.
Another objective of this invention is to provide a pipeline testing method, pipeline test system, pipeline test instruction string generation method and storage medium for automatically generating an instruction string in the interference state without entering conditions.
A further objective of this invention is to provide a pipeline testing method, pipeline test system, pipeline test instruction string generation method and storage medium for automatically and comprehensively generating an instruction string in the interference state without entering the

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