Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1998-03-20
2000-07-18
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714781, H03M 1300
Patent
active
060922338
ABSTRACT:
The present invention provides an apparatus for generating an error locator polynomial from a plurality of partial syndromes. The partial syndromes are generated from a data sector sequentially read from a storage medium. The apparatus comprises discrepancy circuitry, correction polynomial circuitry, connection polynomial circuitry, and a control circuitry. The discrepancy circuitry is configured to receive a selected partial syndrome for generating a discrepancy .DELTA..sup.(k). The correction polynomial circuitry is configured to receive the kth discrepancy .DELTA..sup.(k) from the discrepancy circuitry for generating an associated correction polynomial T(z). The connection polynomial circuitry is configured to receive the kth discrepancy .DELTA..sup.(k) from the discrepancy circuitry for generating an associated connection polynomial .LAMBDA..sup.(k) (z). The control circuitry provides sequencing and control signals to the discrepancy circuitry, the correction polynomial circuitry, and the connection polynomial circuitry in accordance with Berlekamp-Massey algorithm. The connection polynomial circuitry outputs the kth connection polynomial .LAMBDA..sup.(k) (z) as an error locator polynomial when k is equal to the total number of partial syndromes.
REFERENCES:
patent: 4162480 (1979-07-01), Berlekamp
patent: 4845713 (1989-07-01), Zook
patent: 5583499 (1996-12-01), Oh
patent: 5701314 (1997-12-01), Armstrong et al.
patent: 5719884 (1998-02-01), Roth et al.
patent: 5790075 (1999-10-01), Wasada
patent: 5805616 (1998-09-01), Oh
patent: 5805617 (1998-09-01), Im
Jah-Ming Hsu et al., An Area-Efficient VLSI Architecture for Decoding of Reed-Solomon Codes, IEEE, pg. 3291 to 3294, 1996.
Zarowski, Parallel Implementation of the Schur Berlekamp-Massey Algorithm on a Linearly Connected Processor Array, IEEE, pg. 930 to 933, 1995.
S. Lin and D. Costello, Jr., "Error Control Coding", Published Oct. 1982, .COPYRGT. 1983, Prentice-Hall, Inc. Englewood Cliffs, NJ, pp. 167-174.
S. Wilson, "Digital Modulation and Coding", 1996, Ch. 5, pp. 470-472, Prentice-Hall, NJ.
N. Glover and T. Dudley, "Practical Error Correction Design for Engineers", 1991, Cirrus Logic, Inc., CO, Rev. 2.sup.nd Ed.
W.W. Peterson and E.J. Weldon, Jr., "Error-Correcting Codes", 1972, (12.sup.th printing 1994), Mass, Inst. Of Technology, pp. 131-136.
Stephen B. Wicker, "The Decoding of BCH and Reed-Solomon Codes", pp. 203-234, Chap. 9 of "Error Control Systems for Digital Communication and Storage", .COPYRGT. 1995, Prentice-Hall, Inc., Upper Saddle River, NJ.
Adaptec, Inc.
Cady Albert De
Chase Shelly A
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