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Integrated circuit phase partitioned power distribution for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Integrated circuit semiconductor device having built-in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate

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Integrated circuit test apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit test mode with externally forced reference vo

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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Integrated circuit test mode with externally forced...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Integrated circuit test using clock signal modification

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Integrated circuit test using clock signal modification

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Integrated circuit tester having a disk drive per channel

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit tester having pattern generator controlled da

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Integrated circuit tester having pattern generator...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit tester with cached vector memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Integrated circuit tester with multi-port testing functionality

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit tester with software-scaleable channels

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit testing device with dual purpose analog...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit testing method and system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit testing module including data compression

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit testing module including signal shaping...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit testing system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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