Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-10
2007-07-10
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
11227637
ABSTRACT:
An integrated circuit tester for testing an IC device under test (DUT) during a succession of test cycles includes a pattern generator programmed to generate data before each test cycle encoded to specify all test activities to be carried out during the test cycle and to specify for each test activity a time during the test cycle at which the test activity is to be carried out and a DUT IO pin at which the test activity is to be carried out. Multiple programmable tester channels each comprise multiple DUT interface circuits, each of which can be connected to a separate DUT IO pin for carrying out test activities at that DUT IO pin when signaled to do so, and hardware resources programmed by decoding instructions to decode the data from the pattern generator for each test cycle and initiate each specified test activity by signaling the DUT interface circuit that is specified for the test activity at the time specified for the test activity.
REFERENCES:
patent: 5854797 (1998-12-01), Schwartz et al.
patent: 5970073 (1999-10-01), Masuda et al.
patent: 6536006 (2003-03-01), Sugamori
patent: 6678852 (2004-01-01), Tsuto
patent: 6856158 (2005-02-01), Frame et al.
Bedell Daniel J.
Credence Systems Corporation
Kerveros James C
Smith-Hill and Bedell
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