Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-02-14
2006-02-14
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C326S016000, C377S019000
Reexamination Certificate
active
07000162
ABSTRACT:
Disclosed is an integrated circuit device, comprising: a first power rail for supplying power to first latch and a circuit during a first clock phase; a second power rail for supplying power to a second latch during a second clock phase; and the circuit coupled between an output of the first latch and an input of the second latch.
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Bernstein Kerry
Rohrer Norman J.
Van Horn Jody J.
Abraham Esaw
De'cady Albert
International Business Machines - Corporation
LeStrange Michael
Schmeiser Olsen & Watts
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