Integrated circuit test apparatus

Details Integrated circuit test apparatus Integrated circuit test apparatus

2007-02-13

2007-02-13

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

10917403

ABSTRACT:
A fixed-logic signal generated inside an integrated circuit is selectively supplied via selectors (Sm+1 to Sn) to input terminals (INm+1 to INn) of a function macro (1) for receiving signals whose logic levels are fixed to “H” or “L” on at least one test pattern. This eliminates any external input terminal for inputting such fixed-logic signal. When the integrated circuit includes function macros, they can be simultaneously tested with this construction.

REFERENCES:
patent: 4357703 (1982-11-01), Van Brunt
patent: 4635261 (1987-01-01), Anderson et al.
patent: 5329533 (1994-07-01), Lin
patent: 5910181 (1999-06-01), Hatakenaka et al.
patent: 6097206 (2000-08-01), Takano
patent: 6140840 (2000-10-01), Nakamura
patent: 6353565 (2002-03-01), Ito
patent: 6424587 (2002-07-01), Hosada
patent: 6463562 (2002-10-01), Otsuka
patent: 6601199 (2003-07-01), Fukuda et al.
patent: 6968436 (2005-11-01), Kumazawa
patent: 09-166646 (1997-06-01), None

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