Integrated circuit semiconductor device having built-in...

Details Integrated circuit semiconductor device having built-in... Integrated circuit semiconductor device having built-in...

2000-05-08

2003-06-03

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S723000

Reexamination Certificate

active

06574757

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a circuit and method for built-in self-test (BIST) and built-in self-repair (BISR) for a memory circuit in a semiconductor integrated circuit device.
BACKGROUND OF THE INVENTION
Recently, core-based integrated circuit (IC) designs are drawing great attention, as the system-on-a-chip (SOC) design style gains momentum as a new design trend. Accordingly, a memory core or an analog core as well as a central processing unit (CPU) core are frequently used in the IC design. With the trend of SOC design, a complex circuit or system chip such as a CPU requires embedded memories of ever-higher capacity to improve system bandwidth.
Modern technology is capable of achieving high memory capacity while requiring a relatively small die size. Since embedded memories in a circuit have relatively higher complexity and share more signals than other logic blocks, they have higher failure rates. In order to solve this problem, designers commonly add redundancy to the embedded memory.
Semiconductor memory devices are commonly tested by an external memory tester or Automatic Test Equipment (ATE) which physically repairs detected faulty memory cells (for example through laser zapping) through a software repair algorithm, after determining whether the faulty memory cells are repairable or not. To test the SOC according to the above-mentioned method, a core and an embedded memory must be tested separately, and for this reason additional external pins are required. As a result, the SOC test becomes more complex and production cost of the SOC is high.
To address this issue, the SOC commonly comprises a built-in self test (BIST) circuit for performing self-test, and a built-in self repair (BISR) circuit for performing self-repair. The BISR circuit includes a repair algorithm for determining whether the faulty memory cells are repairable or not, and for performing logical repair through software. As described above, the repair method of the BISR circuit is different from the external memory tester or the ATE performing physical repair. An embodiment of above described self-test and self-repair becomes an essential part in recent processor design techniques developing into the SOC. Examples of the BIST circuit and BISR circuit can be found in U.S. Pat. No. 5,920,515 to Shaik et al., issued on July 1999, REGISTER-BASED REDUNDANCY CIRCUIT AND METHOD FOR BUILT-IN SELF-REPAIR IN A SEMICONDUCTOR MEMORY DEVICE; and U.S. Pat. No. 5,987,632 to Irrinki et al., issued on November 1999, METHOD OF TESTING MEMORY OPERATIONS EMPLOYING SELF-REPAIR CIRCUITRY AND PERMANENTLY DISABLING MEMORY LOCATIONS.
Generally, repair methods employing the redundancy cells determine which word line and bit line of the faulty memory cells are replaced to the redundancy cells through a depth first search (DFS), case by case, by constructing a binary search tree with word lines (i.e., row addresses) and bit lines (i.e., column addresses) of the faulty memory cells via software. In this case, the technique consumes O(2
n
) of test time, meaning that the operation takes 2
n
of time, assuming the time required to execute one operation (for example, multiplication) is n. The required time forms an exponential function against the row and column redundancies and distribution of the faulty memory cells. Thus, the repair method is not efficient when the number of the redundancies is great and when the memory includes many faulty memory cells. This problem is referred to as an “NP-completeness” problem. To solve the problem, a heuristic method is used. The heuristic method solves a given problem through an experiential knowledge obtained by trial and error. If any algorithm is adopted in the NP-completeness problem, it may efficient to restrict a range of the problem to within extremely narrow limits. In that case, it is impossible to embody the NP-completeness problem to hardware without restricting the limits.
For this reason, some SOCs embedding the BISR circuit restrict the limits to be repaired. For example, the numbers of the row and column redundancies are restricted to within 1, respectively. In case that the respective redundancies are one or one pair, the structure of the BISR circuit becomes simple. In that case, the SOC has a restriction that the SOC can repair only one row and one column.
However, considering the tendency that SOC requires an embedded memory with much higher capacity, additional redundancies are required to repair any additional faulty memory cells occurring in the embedded memory. If the faulty memory cells of the embedded memory are not repaired completely, the reliability of the SOC can be adversely affected by faulty memory cells of the relatively inexpensive embedded memory, even though the relatively expensive core such as a central processing unit (CPU) is fault free.
SUMMARY OF THE INVENTION
A novel BISR circuit and a repair method are therefore required to repair the faulty memory cells of an embedded memory having multiple redundancies, in a more precise manner.
It is therefore an object of the present invention to provide an integrated circuit semiconductor device having a BISR circuit for an embedded memory with multiple redundancies.
It is another object of the invention to provide a repair method of a BISR circuit for an embedded memory with multiple redundancies.
In order to attain the above objects, according to an aspect of the present invention, there is provided an integrated circuit semiconductor device comprising an embedded memory including multiple row and column redundancies; a built-in self-test circuit for detecting faulty memory cells of the memory; and a built-in self-repair circuit for storing the detected faulty memory cell information by splitting information into row information and column information, determining repair methods of the faulty memory cells in response to the row and column information, and generating repaired addresses to the memory in response to the determined repair methods.
The built-in self-repair circuit preferably includes a built-in self-repair controller for controlling operation of the built-in self-repair circuit; a first data storing means including a plurality of entries having a plurality of data fields, for storing row addresses of the faulty memory cells and the number of the faulty memory cells occurring at a common row address; a first logic unit for storing the row addresses and the number of the faulty memory cells to the first data storing means under control of the built-in self-repair controller; a second data storing means including a plurality of entries having a plurality of data fields, for storing column addresses of the faulty memory cells and the number of the faulty memory cells occurring at the same column address; a second logic unit for storing the column addresses and the number of the faulty memory cells to the second data storing means under control of the built-in self-repair controller; a third logic unit for storing entry locations of opposite data storing means storing column and row addresses corresponding to row and column addresses of the first and second data storing means, and for decreasing the number of faulty memory cells stored at the entry locations of the opposite data storing means under control of the built-in self-repair controller, and an address checker for generating repaired row and column addresses to the memory in response to the row and column addresses of the faulty memory cells under control of the built-in self-repair controller.
The built-in self-repair circuit preferably first determines the repair methods of either of the first data storing means or the second data storing means, depending on which of the first and second data storing means has fewer entries. The built-in self-repair circuit may also determine the repair methods of the first or second data storing means by selecting entries composing the first or second data storing means in order of the number of the stored faulty memory cells.
The third logic unit preferably decreases the number o

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