Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-08-17
2002-12-03
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06490701
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to testing integrated circuits having internally generated reference voltages.
BACKGROUND OF THE INVENTION
Integrated circuits, such as memory devices, require extensive testing during fabrication to insure that a finished circuit is fully operational. This testing is performed during various stages of fabrication and may be tested while it is still part of an integrated circuit wafer. This testing is usually performed using an integrated circuit probe card which physically connects a tester to probe pads, and other electrical conductors, provided on each circuit die. The tests performed are numerous and often depend upon the type of device fabricated. These tests are often performed by placing the integrated circuit in a specific test mode of operation. While manufacturers of integrated circuits extensively test their devices using these test modes, it is desired to prohibit an end-user from placing a completed device in a test mode. As such, various methods have been devised to allow testing during manufacturing while prohibiting accidental initiation during use. These methods include, but are not limited to, electronic keys and super voltages, as known to those skilled in the art.
Some integrated circuits include voltage generator circuits which provide an internal reference voltage. For example, an integrated circuit memory device can include an internal circuit for providing a reference voltage. Prior to testing, therefore, the integrated circuit memory device must be capable of providing the internal reference voltage. The voltage generator circuit, however, often requires extensive programming prior to providing a valid reference voltage. This requirement provides a dilemma during testing. That is, a defective memory device must first be programmed to provide the internal reference voltage before it is determined that the memory device is defective. Because the procedure for setting the internal reference voltage requires numerous seconds (up to 20 seconds is common), valuable time is wasted during testing.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method of testing an integrated circuit which does not require an internal reference voltage generator to be set prior to testing.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuit testing and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A method is described which allows an integrated circuit to be tested prior to setting an internal reference voltage generator.
In particular, the present invention describes a method of testing an integrated circuit. The method comprises the steps of placing the integrated circuit in a test mode, decoupling an input connection configured to receive an input command signal, and setting a latch circuit to a predetermined state in response to the test mode to provide a substitute signal for the input command signal. An external reference voltage is coupled to the input connection. The method further comprises testing the integrated circuit using the external reference voltage, and setting an internal reference voltage generator circuit to provide an internal reference voltage if the integrated circuit passes the step of testing.
In another embodiment, a method of testing a flash memory device is described. The method comprises the steps of placing the flash memory device in a test mode in response to signals provided on input connections, decoupling a BYTE input connection configured to receive an input command signal identifying an operating data width, and setting a latch circuit to a predetermined state in response to the test mode to provide a substitute signal for the input command signal. The method further comprises coupling an external reference voltage to the input connection, testing the flash memory device using the external reference voltage, and setting an internal reference voltage generator circuit to provide an internal reference voltage if the flash memory device passes the step of testing.
In yet another embodiment, a memory device comprises an array of memory cells, a control circuit for operating the memory device in a test mode in response to external input signals, a control input pin adapted to receive a control signal during non-test mode operations, and a latch circuit coupled to the control input pin and adapted to provide a substitute signal for the control signal during test mode operation. A programmable reference voltage generator circuit is provided and configured to provide an internal reference voltage. Bypass circuitry is coupled to the control input pin and adapted to receive an externally supplied reference voltage during non-test mode operations. The externally supplied reference voltage is substituted for the internal reference voltage while the programmable reference voltage generator circuit is not programmed.
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Papaliolios A.
Roohparvar Frankie Fariborz
De'cady Albert
Schwegman Lundberg Woessner & Kluth P.A.
Torres Joseph D.
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