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Timing generator and semiconductor testing apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Timing generator and semiconductor testing device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Timing generator and test apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Timing generator for testing semiconductor storage devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Timing verifying system in which waveform slew is considered

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Timing-aware test generation and fault simulation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Toggle memory burst

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Tolerating memory errors by hot ejecting portions of memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Tool to reconfigure pin connections between a DUT and a tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Tool to reconfigure pin connections between a DUT and a tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Total configuration memory cell validation built in self...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Trace-ahead method and apparatus for determining survivor...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Traceback buffer management for VLSI Viterbi decoders

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Traceback processor for use in a trellis-coded modulation decode

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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Traceback stage for a viterbi decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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Track buffer in a parallel decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Tracking a code modulated signal

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Tracking health of integrated circuit structures

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Trading propensity-based clustering of circuit elements in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Trading propensity-based clustering of circuit elements in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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