Timing generator and semiconductor testing apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S738000, C714S703000, C714S707000, C714S739000, C714S745000, C714S814000, C327S265000, C327S279000, C327S286000, C327S170000, C327S107000, C375S371000, C375S226000, C702S069000, C370S516000

Reexamination Certificate

active

07665004

ABSTRACT:
A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced. There are included a counter for performing a counting operation synchronized with a reference clock signal: a timing memory for outputting respective data corresponding to the quotient and remainder resulting from dividing the time from the front of a basic period until a generation of a timing edge by the period of the reference clock signal: a coincidence detecting circuit for outputting a signal that exhibits a high level when the count value of the counter coincides with the quotient: a jitter generating circuit for outputting as a jitter amplitude value: adders for adding a time corresponding to the remainder and a time represented by the jitter amplitude value outputted from the jitter generating circuit: and a variable delay circuit for delaying the output signal from the coincidence detecting circuit by the time represented by the addition result of the adders and outputting the delayed output signal.

REFERENCES:
patent: 3916329 (1975-10-01), Hekimian et al.
patent: 5394106 (1995-02-01), Black et al.
patent: 6998893 (2006-02-01), Takahashi et al.
patent: 7230981 (2007-06-01), Hill
patent: 2005/0044463 (2005-02-01), Frisch
patent: 2005/0097420 (2005-05-01), Frisch et al.
patent: 54-099539 (1979-08-01), None
patent: 08-050156 (1996-02-01), None
patent: 11-23666 (1999-01-01), None
patent: 2000-2757 (2000-01-01), None

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