Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1997-02-18
1999-11-16
Grant, William
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
G06F 1110
Patent
active
059876379
ABSTRACT:
In a traceback unit for an M-step Viterbi decoder for a convolutionally encoded data stream, each of the traceback stages has a group of K input wires representing K possible candidate states. A bank of K multiplexers selects one of 2.sup.M of the input wires according to M bits of traceback data. The K multiplexer outputs feed a succeeding traceback stage. M groups of K wires carry the traceback data, with each wire being connected to a selection line of each multiplexer. At the output of the traceback unit an identification circuit identifies a subgroup of the K possibilities which has a maximum number of candidate states remaining therein. The arrangement obviates the need for retiming between every traceback stage.
REFERENCES:
patent: 4709377 (1987-11-01), Martinez et al.
patent: 4713829 (1987-12-01), Eyuboglu
patent: 4748626 (1988-05-01), Wong
patent: 5162797 (1992-11-01), Murata et al.
patent: 5187675 (1993-02-01), Dent et al.
patent: 5233630 (1993-08-01), Wolf
patent: 5408502 (1995-04-01), How
patent: 5416787 (1995-05-01), Kodama et al.
patent: 5465275 (1995-11-01), Blaker et al.
patent: 5497401 (1996-03-01), Ramaswamy et al.
patent: 5506636 (1996-04-01), Patel et al.
patent: 5712880 (1998-01-01), Rim et al.
Cypher, Robert. Generalized Trace-Back Techniques for Survivor Memory Management in the Viterbi Algorithm. Journal of VLSI Signal Processing, Jan. 1993 pp. 85-94.
Paaske, E. S. Pedersen and J Sparse. An Area-Efficient Path Memory Structure for VLSI Implmentation of High Speed Viterbi Decoders. Integration, the VLSI Journal, Nov. 1991 pp. 79-91.
European Telecommunciations Standards Institute "European Telecommunication Standard: Digital Broadcasting Systems for Television, Sound and Data Services; Framing Structure, Channel Coding and Modulation for Digital Television." Valbonne, France. May 1996, pp. 1-40.
Fettweis, Gerhard and Heinrich Meyr, "Parallel Viterbi Algorithm Implementation: Breaking the ACS-Bottleneck," IEEE Transaction on Communications, vol. 37, No. 8, Aug. 1989.
J. Sparso et al., "An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type Structures," IEEE Journal of Solid-State Circuits, vol. 26, No.2 Feb. 1991.
Le Goff, Stephane. Alain Glavieux and Cluade Berrou. "Turbo-Codes and High Spectral Efficiency Modulation." Telecom Bretagne, France Telecom University, IEEE 0-7802-1825-0/94, 1994. pp. 645-649.
Troung, T.K. et al., "A VLSI Design for a Trace-Back Viterbi Decoder," IEEE Transactions on Communications, vol. 40, No. 3, Mar. 1992.
Bollella Donald
Discovision Associates
Grant William
Rapp Chad
LandOfFree
Traceback stage for a viterbi decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Traceback stage for a viterbi decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Traceback stage for a viterbi decoder will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1338870