Timing generator and semiconductor testing device

Details Timing generator and semiconductor testing device Timing generator and semiconductor testing device

2007-07-03

2007-07-03

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S815000, C713S401000

Reexamination Certificate

active

11126038

ABSTRACT:
A timing generator f or a semiconductor test device reduces pattern-dependent jitters and timing errors of timing pulse signals. In the timing generator, a delaying circuit (variable delaying means, clock signal delaying circuit) is disposed on an input terminal side of a clock signal of a signal input/output circuit having the flip-flop (reference signal delaying means) which outputs an output signal in accordance with an input timing of the delayed clock signal. The clock signal is delayed by the delaying circuit. The clock signal delaying circuit may be replaced with a phase locked loop circuit.

REFERENCES:
patent: 6829715 (2004-12-01), Chiao et al.
patent: 6928570 (2005-08-01), Fukuda
patent: 7069458 (2006-06-01), Sardi et al.
patent: 7107477 (2006-09-01), Singh et al.
patent: 03-090874 (1991-04-01), None
patent: 05-087878 (1993-04-01), None
patent: 10-319097 (1998-12-01), None
patent: 11-125660 (1999-05-01), None
patent: 2001-133525 (2001-05-01), None

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