LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery,Pulse or data error handling

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Scrambling apparatus, method thereof, descrambling apparatus, an

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...

Patent

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Screening for errors in data transmission systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Screening for undetected errors in data transmission systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Screening for undetected errors in data transmission systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Patent

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SDRAM address error detection method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Second stage SOVA detector

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Second stage SOVA detector

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Sector-coding technique for reduced read-after-write operations

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Secure scan design

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Secure software system and related techniques

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Patent

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Segmented addressable scan architecture and method for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Segmented algorithmic pattern generator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Segmented algorithmic pattern generator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Segmented compaction with pruning and critical fault...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Segmented scan chains with dynamic reconfigurations

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Select and enable leads connecting IC taps and embedded...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Selectable JTAG or trace access with data store and output

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Selectable JTAG or trace access with data store and output

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Selectable sense amplifier delay circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Selecting a scan topology

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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