Scrambling apparatus, method thereof, descrambling apparatus, an

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...

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380210, G06F 1100, H04N 7167

Patent

active

061580260

ABSTRACT:
A G circuit is based on a matrix of a generated polynomial for generating an M sequence of eight degrees. The matrix is squared and thereby a G.sup.2 circuit is obtained. 16-bit data is divided into high order eight bits and low order eight bits. The high order eight bits and the low order eight bits are supplied to first input terminals of two Ex-OR circuits. At first, a terminal is selected so that ID of data is extracted. The G circuit and the G.sup.2 circuit designate the start point of the M sequence. Next, a terminal is selected so that output data of the G.sup.2 circuit is fed back. Output data of the G.sup.2 circuit 113 and the G circuit are supplied to the second input terminals of the Ex-OR circuits. In each of the two Ex-OR circuits, data supplied to the first input terminal and the second input terminal is Ex-ORed. Thus, data of 16 bits is descrambled.

REFERENCES:
patent: 3808536 (1974-04-01), Reynolds
patent: 5267316 (1993-11-01), Merino Gonzalez et al.
patent: 5471531 (1995-11-01), Quan

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