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Selected: P

Providing a header checksum for packet data communications

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Providing data integrity for data streams

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Providing data integrity for data streams

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Providing error correction coding for probed data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Providing high availability in a PCI-Express™ link in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Providing pseudo-randomized static values during LBIST...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Providing test vectors with pattern chaining definition

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Providing trusted access to a JTAG scan interface in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Provision of debug via a separate ring bus in a data...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Prunable S-random block interleaver method and corresponding...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Pruned bit-reversal interleaver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Pseudo bus agent to support functional testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pseudo fail bit map generation for RAMS during component...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Pseudo product code encoding and decoding apparatus and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Pseudo random optimized built-in self-test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pseudo-random wait-state and pseudo-random latency components

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pseudo-scan testing using hardware-accessible IC structures

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pulse generation circuit and semiconductor tester that uses...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pulse interference testing in a CDMA communication system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Pulsed flop with scan circuitry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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