Pseudo fail bit map generation for RAMS during component...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S723000

Reexamination Certificate

active

07051253

ABSTRACT:
According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses. The method executes a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test. The method includes determining a fail string for the device including pass/fail results for the test pattern, and combining the pass/fail results in the fail string.

REFERENCES:
patent: 5588115 (1996-12-01), Augarten
patent: 5961653 (1999-10-01), Kalter et al.
patent: 6643807 (2003-11-01), Heaslip et al.
patent: 6651206 (2003-11-01), Hosokawa et al.
Schanstra et al., Semiconductor manufacturing process monitoring using built-in self-test for embedded memories, Oct. 1998, International Test Conference proceedings 1998, pp 872-881.
NN9111377 (Reconfigurable Signature Generator. IBM Tech. Disclosure Bulletin, vol. # 34 Issue # 6, pp. 377-380, Nov. 1, 1991).
Schanstra, Ivo, et al.,Semiconductor Manufacturing Process Monitoring Using Built-In Self-Test for Embedded Memories.
Vollrath, Jorg, et al.,Compressed Bit Fail Maps for Memory Fail Pattern Classification.
Vollrath, Joerg,Tutorial: Characterizing SDRAMS.

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