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Models and technique for automated fault isolation of open...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modem using phase coherence to adapt for missing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Modem-assisted bit error concealment for audio...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Modified branch metric calculator to reduce interleaver...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Modified chase combining for hybrid automatic repeat request

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Modified Reed-Solomon error correction system using (W+i+1)-bit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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Modified Reed-Solomon multiplication

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Modified soft output Viterbi algorithm for truncated trellis

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Modified viterbi detector for jitter noise dominant channels

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Modifying a test pattern to control power supply noise

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modifying circuit designs running from both edges of clock...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modular architecture for memory testing on event based test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modular re-useable bus architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Modular test controller with BIST circuit for testing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Modular test controller with BIST circuit for testing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Modular turbo decoder for expanded code word length

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Modular/re-configurable test platform

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modulation detection method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Module based flexible semiconductor test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Module for generating circuits for decoding convolutional...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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