Module for generating circuits for decoding convolutional...

Details Module for generating circuits for decoding convolutional... Module for generating circuits for decoding convolutional...

2001-10-11

2008-07-15

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S755000, C714S781000

Reexamination Certificate

active

07401284

ABSTRACT:
The present invention relates to a module50for generating integrated decoding circuits for use, in particular, in turbo devices, to the method for defining the characteristics of and generating convolutional decoding circuits, and to the circuit that can be obtained with said module50.The module50is parametric and, thanks to this feature, makes it possible to generate decoding circuits having different performance characteristics which are such that they can be used in turbo devices employing different decoding modes and different architectures. In addition, the module50makes it possible to generate decoding circuits whose distinguishing feature is that they can manage a plurality of generator polynomials selectively and can thus also be used in asymmetrical turbo devices.

REFERENCES:
patent: 6484283 (2002-11-01), Stephen et al.
Scalable Architectures for High Speed Channel Decoding by Dawid et al, (IEEE 1994).
Efficient Scalable Architecture for Viterbi Decorders by Bitterlich et al. (IEEE 1993).
VLSI Architectures for Turbo Codes by Masera et al. (IEEE 1999).
Implementation and Performance of a Turbo/Map Decoder by Stephen S. Pietrobon, 1998 John Wiley & Sons, Ltd., pp. 23 to 46.

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