Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-04-08
2008-04-08
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000, C365S201000
Reexamination Certificate
active
10304506
ABSTRACT:
A modular test controller with a built-in self-test (BIST) circuit for testing an embedded DRAM (eDRAM) circuit is provided. The test controller includes a built-in self-test (BIST) core for performing tests, the BIST core including proven testing algorithms; a selectable tester interface for interfacing the BIST core with an external tester; and a selectable eDRAM interface for interfacing the BIST core with an eDRAM, the eDRAM including a plurality of memory cells for storing data. The present invention allows semiconductor device designers to keep to one testflow and reuse a proven BIST core over multiple ASIC (Application Specific Integrated Circuits) products/generations.
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Chung Phung My
Edell Shapiro & Finnan LLC
Infineon - Technologies AG
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