Modified Reed-Solomon error correction system using (W+i+1)-bit

Details Modified Reed-Solomon error correction system using (W+i+1)-bit Modified Reed-Solomon error correction system using (W+i+1)-bit

1997-01-23

1999-09-07

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714785, H03M 1300

Patent

active

059481170

ABSTRACT:
An error correction system includes an encoder that uses a modified Reed-Solomon code to encode w-bit data symbols over GF(2.sup.w+i) and form a preliminary code with d-1 (w+i+1)-bit redundancy symbols. The preliminary code word is modified as necessary to set for each symbol a selected i bits to the same value as a corresponding i+1.sup.st bit. The preliminary code word also includes R pseudo redundancy symbols that are required for decoding the modified code word. The i+1 bits are then truncated from each of the code word symbols, to form a code word with w-bit symbols. The Galois Field GF(2.sup.w+i) is selected such that the elements of the field can be represented by (w+i+1)-bit symbols that are determined by a polynomial h(x) modulo an irreducible polynomial p(x), which is

REFERENCES:
patent: 4413339 (1983-11-01), Riggle et al.
patent: 4856003 (1989-08-01), Weng

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