Layout for a semiconductor memory device having redundant elemen

Details Layout for a semiconductor memory device having redundant elemen Layout for a semiconductor memory device having redundant elemen

1999-10-08

2000-12-19

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

714733, 714710, G11C 2900

Patent

active

061638609

ABSTRACT:
The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more "planes." Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory. As a result, the present invention saves on the number of lines required to intercouple the compare circuits to the redundant rows/columns.

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