Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-04-29
2010-06-01
Chaudry, M. Mujtaba K (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S006130, C714S800000, C714S804000
Reexamination Certificate
active
07730377
ABSTRACT:
A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a probability value estimate and a check node value estimate, the probability value estimate and the check node value estimate associated with a parity check matrix. The system also comprises a plurality of parity check update modules (PCUMs) in parallel with each other, coupled to the first adder module and adapted to update the check node value estimate, and a second adder module coupled to the plurality of PCUMs and adapted to update the probability value estimate using the extrinsic estimate and the updated check node value estimate. The PCUMs process at least some columns of at least some rows of the parity check matrix in a serial fashion.
REFERENCES:
patent: 4404674 (1983-09-01), Rhodes
patent: 6633856 (2003-10-01), Richardson
patent: 7237181 (2007-06-01), Richardson
patent: 2003/0023917 (2003-01-01), Richardson
patent: 2004/0034828 (2004-02-01), Hocevar
patent: 2004/0194007 (2004-09-01), Hocevar
patent: 2006/0015802 (2006-01-01), Hocevar
Guilloud, R. et al., “-Min Decoding Algorithm Of Regualr And Irregular LDPC Codes,” International Symposium On Turbo Codes, Brest, France, Sep. 1-5, 2003, pp. 451-454.
Gunnam, K. et al., “An LDPC Decoding Schedule For Memory Access Reduction,” IEEE International Conference On Acoustics, Speech And Signal Processing (ICASSP), Montreal, May 2004, pp. V:173-176.
Jones, C. et al., “Approximate-Min* Constraint Node Updating For LDPC Code Decoding,” IEEE Military Communications Conference (MILCOM), Oct. 2003, pp. 157-162.
Mansour, M. M., et al., “A Novel Design Methodology for High Performance Programmable Decoder Cores for AA-LDPC Codes,” IEEE Workshop On Signal Process Systems (SIPS), Aug. 2003, pp. 29-34.
Olcer, S., “Decoder Architecture for Array-code Based LDPC Codes,” IEEE Global Telecomm. Conf. (GLOBECOM), San Francisco, CA., Dec. 2003, pp. 2046-2050.
Rosenthal, J. et al., “Constructions Of Regular And Irregular LDPC Codes Using Ramanujan Graphs And Ideas From Margulis,” Proceedings IEEE International Symposium On Information Theory, Washington, D.C., Jun. 2001, p. 4.
Sridhara, D. et al., “Low Density Parity Check Codes From Permutation Matrices,” Conference On Information Sciences And Systems., The John Hopkins University, Mar. 2001, one page.
Zhong, H. et al., “Design Of VLSI Implementation-Oriented LDPC Codes,” IEEE Vehicular Technical Conference (VTC Fall), Oct. 2003, pp. 670-373.
Hocevar, Dale E., U.S. Appl. No. 11/056,755, filed Feb. 11, 2005, 21 pages, including 5 sheets of formal drawings.
Ahmed Enam
Brady W. James
Chaudry M. Mujtaba K
Shaw Steven A.
Telecky , Jr. Frederick J.
LandOfFree
Layered decoding of low density parity check (LDPC) codes does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Layered decoding of low density parity check (LDPC) codes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layered decoding of low density parity check (LDPC) codes will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4241172