Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-10-25
2003-11-25
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S073100
Reexamination Certificate
active
06654920
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to built-in-self-testing for integrated circuits and are more particularly directed to a testing controller that is readily adaptable to various different integrated circuit designs.
The complexity of modern integrated circuit applications has greatly increased the need for thoroughly testing these devices once they are constructed. Typically, such testing is performed at the beginning of the life cycle of the device, and provided the device successfully meets the testing criteria, it is then shipped for eventual use in an application. To facilitate this testing, testing circuitry is often included on the integrated circuit and the use of such circuitry is commonly referred to as a built-in-self-test (“BIST”). As further explored later, BIST circuitry often includes numerous storage registers connected to one another to form what is referred to in the art as a scan chain, where each register in the chain is commonly implemented as a flip-flop. To perform a test, test patterns are written into the scan chain registers and the state of the integrated circuit is determined to evaluate whether the state properly reflects the appropriate operation of the integrated circuit given the test patterns. Further in this regard, prior to the advent of BIST systems scan chains as described above were used for testing through use of a tester, external from the integrated circuit, to generate the various test patterns that were then scanned into the scan chain(s) of the integrated circuit for testing. More recently, however, BIST has been developed whereby many contemporary integrated circuits include on-chip BIST controllers which themselves generate the test patterns, thereby considerably reducing the need for an off-chip tester. BIST also has various related technologies, such as logic BIST (or “LBIST”) for testing combinational logic or memory BIST for testing memory circuits.
By way of further background, yet another more recent feature in the field of LBIST systems has been the addition to LBIST of an architecture which is referred to in the art by its acronym STUMPS, thereby abbreviating the terms “self-test using MISR/parallel SRSG,” where MISR is an abbreviation for multiple input signature register and SRSG is an abbreviation for shift register sequence generator. As further explored later, a STUMPS architecture includes various different scan paths referred to as “channels,” where each channel is again formed using multiple interconnected storage registers, such as flip-flops. In a scan mode, an LBIST controller loads the multiple channels with respective test patterns, and the device is then switched into its functional mode and operated for one or more clock cycles, thereby changing the state at likely many of the nodes of the circuit. The state changes include changes that will affect what is stored in one or more of the scan channel registers. Thereafter, the device is returned to the scan mode, and the data in the scan channels are shifted out and evaluated to determine if the expected result are produced, thereby either confirming proper device operation or evidencing a problem with the device. In addition to evaluating the scan channel data, other device states and signals may be evaluated (such as via integrated circuit output pins) to determine if the device operated properly in response to the test.
While the STUMPS architecture has provided considerable advancement in BIST and LBIST effectiveness, the present inventors have recognized that it includes a considerable drawback. Specifically, further arising in connection with the multiple scan channels in a STUMPS architecture is the fact that the channels commonly have a different number of scan registers (or “cells”). In the art, it is said that these number of cells form the length of each scan channel and, thus, applying this terminology to the preceding then it may be stated that the scan channels are of different lengths. In any event, given this aspect the length of the longest scan channel must be known to the LBIST controller so that it may properly load the channels with scan test patterns and properly control the LBIST testing once the test patterns are loaded. In the prior art and to accommodate this requirement, the length of the longest scan channel is hard coded into the LBIST controller at the time the controller is designed and formed. However, as with other aspects of circuit design, when a value is hard coded into an integrated circuit, it restricts the flexibility of the circuit as related to that value. For example, an LBIST controller once formed and hard coded in this manner is restricted for use with a STUMPS architecture having a longest scan channel equal to the hard coded value. As another example, if the length of the longest scan channel is changed during development of the integrated circuit, then attention also must be properly made to ensure that the planned hard coded value is also changed so as to achieve proper operation of the LBIST controller.
Given the preceding, the present inventors set forth below a preferred embodiment for LBIST STUMPS architectures, and which seeks to address, reduce, and potentially eliminate the drawbacks set forth above.
BRIEF SUMMARY OF THE INVENTION
In a preferred embodiment, there is an integrated circuit comprising combinational circuitry. The integrated circuit further comprises a plurality of scan channels. Each of the plurality of scan channels comprises a number of scan elements. For any of the plurality of scan channels having a number of scan elements greater than one element, the scan channel comprises a first element in the scan channel and a last element in the scan channel. For any of the plurality of scan channels having a number of scan elements equal to one element, the one element is both a first element and a last element in the scan channel. Further, selected ones of the scan elements are coupled to affect operation of the combinational circuitry. The integrated circuit further comprises circuitry for coupling a predetermined pattern into the first element of each of the plurality of scan channels and circuitry for detecting the predetermined pattern in the last element of each of the plurality of scan channels. Finally, the integrated circuit further comprises circuitry for determining, in response to circuitry for detecting, the number of scan elements in a longest of the plurality of scan channels. Other circuits, systems, and methods are also disclosed and claimed.
REFERENCES:
patent: 4283620 (1981-08-01), Drescher et al.
patent: 6442723 (2002-08-01), Koprowski et al.
Rajski et al. “Comparative study of CA-based PRPGs and LFSRs with phase shifters; Mentor Graphics Corp., Wilsonwille, OR 17th IEEE VLSI Test Symposium, 1999. PRoceedings; Pp: 236-245; Apr. 29, 1999”.*
Kemnitz “Synthesis of locally exhaustive test pattern generators; VLSI Test Symposium, 1995. Proceedings., 13th IEEE , Pp. 440-445; 30 Apr.-May 30, 1995”.
Fryars Anthony
Hetherington Graham G.
Brady III W. James
De'cady Albert
Lamarre Guy
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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