Layout for semiconductor memory device wherein intercoupling lin

Details Layout for semiconductor memory device wherein intercoupling lin Layout for semiconductor memory device wherein intercoupling lin

1997-08-14

2000-01-25

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

G06F 1120

Patent

active

060188111

ABSTRACT:
The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more "planes." Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory. As a result, the present invention saves on the number of lines required to intercouple the compare circuits to the redundant rows/columns.

REFERENCES:
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 4471472 (1984-09-01), Young
patent: 4573146 (1986-02-01), Graham et al.
patent: 4601019 (1986-07-01), Shah et al.
patent: 4837747 (1989-06-01), Dosaka et al.
patent: 5257229 (1993-10-01), McClure et al.
patent: 5270974 (1993-12-01), Reddy
patent: 5295102 (1994-03-01), McClure
patent: 5299164 (1994-03-01), Takeuchi et al.
patent: 5303192 (1994-04-01), Baba
patent: 5307316 (1994-04-01), Takemae
patent: 5340679 (1994-08-01), Hiltebeitel et al.
patent: 5353253 (1994-10-01), Nakajima
patent: 5355340 (1994-10-01), Coker et al.
patent: 5377146 (1994-12-01), Reddy et al.
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5396124 (1995-03-01), Sawada et al.
patent: 5455798 (1995-10-01), McClure
patent: 5466693 (1995-11-01), Okamoto
patent: 5491664 (1996-02-01), Phelan
patent: 5528539 (1996-06-01), Ong et al.
patent: 5537665 (1996-07-01), Patel et al.
patent: 5574729 (1996-11-01), Kinoshita et al.
patent: 5577050 (1996-11-01), Bair et al.
patent: 5602786 (1997-02-01), Pascucci et al.
patent: 5617365 (1997-04-01), Horiguchi et al.
patent: 5659509 (1997-08-01), Golla et al.
patent: 5691945 (1997-11-01), Liou et al.
patent: 5790462 (1998-08-01), McClure
patent: 5809225 (1998-09-01), Ohsawa et al.
"FPM DRAMs" DRAM Data Book, Chapter 2, Micron Technology, Inc., pp. 2-1 to 2-14, 1995.

Affiliated with

Also associated with

Rating

Layout for semiconductor memory device wherein intercoupling lin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Layout for semiconductor memory device wherein intercoupling lin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout for semiconductor memory device wherein intercoupling lin will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2324053