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Flexible method of error protection in communications systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Flexible multi-bit per symbol rate encoding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Flexible rate and punctured zigzag codes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Flexible row redundancy system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Flexible row redundancy system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Flexible scan architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flexible test environment for automatic test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flexible test environment for automatic test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flip flop circuit and apparatus using a flip flop circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flip flop circuit and apparatus using a flip flop circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flip flop circuit for scan test with two latch circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Flip-flop and scan path circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flip-flop circuit for capturing input signals in priority order

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flip-flop, shift register, and scan test circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Folding systolic architecture for comma-free reed-solomon...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Format control circuit and semiconductor test device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Format for randomized data block in a storage device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Formatting method and apparatus for a direct access storage...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Forming of error correction data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Formulaic flexible collision-free memory accessing for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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