Formulaic flexible collision-free memory accessing for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S773000

Reexamination Certificate

active

08065588

ABSTRACT:
Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping,MOD,C,W) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (π) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors. This memory mapping allows collision-free reading and writing of updated information (as updated using parallel implemented turbo decoder) into memory banks.

REFERENCES:
patent: 5406570 (1995-04-01), Berrou et al.
patent: 5446747 (1995-08-01), Berrou
patent: 5563897 (1996-10-01), Pyndiah et al.
patent: 5950220 (1999-09-01), Quach
patent: 6065147 (2000-05-01), Pyndiah et al.
patent: 6119264 (2000-09-01), Berrou et al.
patent: 6122763 (2000-09-01), Pyndiah et al.
patent: 6603412 (2003-08-01), Gatherer et al.
patent: 7020827 (2006-03-01), Gatherer et al.
patent: 7305593 (2007-12-01), Andreev et al.
patent: 1288292 (2001-03-01), None
patent: 0 735 696 (1996-10-01), None
patent: 0 735 696 (1999-01-01), None
patent: 2675970 (1992-10-01), None
C. Berrou, Y. Saouter, C. Douillard, S. Kerouédan, and M. Jézéquel, “Designing good permutations for turbo codes: towards a single model,” 2004 IEEE International Conference on Communications (ICC), vol. 1, pp. 341-345, Jun. 20-24, 2004.
O. Y. Takeshita, “On maximum contention-free interleavers and permutation polynomials over integer rings,” IEEE Trans. Information Theory, vol. 52, No. 3, Mar. 2006, pp. 1249-1253 (5 pages).
A. Tarable, S. Benedetto and G. Montorsi “Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures,” IEEE Trans. on Information Theory, vol. 50, No. 9, pp. 2002-2009, Sep. 2004 (8 pages).
A. Nimbalker, T. E. Fuja, D. J. Costello, Jr. T. K. Blankenship and B. Classon, “Contention-Free Interleavers,” IEEE ISIT 2004, Chicago, USA, Jun. 27-Jul. 2, 2004.
Ericsson, Motorola, “QPP interleaver parameters,” 3GPP TSG RAN WG1 #47bis R1-070484 (5 pages).
Alberto Tarable, Sergio Benedetto and Guido Montorsi, “Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures,” IEEE Transactions on Information Theory, vol. 50, No. 9, Sep. 2004, XP011118021, pp. 2002-2009, ISSN: 0018-9448.
Broadcom, “Formulaic Collision-free Memory Accessing for Parallel Turbo Decoding with ARP Interleave,” TDOC R1-070172 of 3GPP TSG RAN WG 1 #47, Jan. 19, 2007, XP-002475290, pp. 1-12.
Jaeyoung Kwak and Kwyro Lee, “Design of Dividable Interleaver for Parallel Decoding in Turbo Codes,” Electronics Letters, IEEE Stevenage, GB, vol. 38, No. 22, Oct. 24, 2002, XP-006019128, pp. 1362-1364. ISSN: 0013-5194.
Aliazam Abbasfar and Kung Yao, “An Efficient and Practical Architecture for High Speed Turbo Decoders,” Proceedings of Vehicular Technology Conference VTC 2003, Oct. 6, 2003, XP-010700880, vol. 1, pp. 337-341, ISSN: 0-7803-7954-3.
Motorola, “Eliminating Memory Contentions in LTE Channel Coding,” TDOC R1-062080 of 3GPP TSG RAN WG1#46, Aug. 28, 2006, XP-002475296, pp. 1-4.
Oscar Y. Takeshita, “On Maximum Contention-Free Interleavers and Permutation Polynomials Over Integer Rings,” IEEE Transactions on Information Theory, IEEE USA, vol. 52, No. 3, Mar. 2006, XP-002473953, pp. 1249-1253, ISSN: 0018-9448.

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