Folding systolic architecture for comma-free reed-solomon...

Details Folding systolic architecture for comma-free reed-solomon... Folding systolic architecture for comma-free reed-solomon...

2005-08-09

2005-08-09

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S784000

Reexamination Certificate

active

06928600

ABSTRACT:
A kind of folding systolic array architecture for a CFRS decoding circuit that applies to a cell search in a wideband code division multiple access system. The invention involves using a systolic array for its decoding circuit and using a kind of folding technology to reduce the area of the systolic array. The systolic array for the decoding circuit comprises an input pattern generator, a processing element array designed in the form of a systolic array and a boundary processing element array. Given the skewed-form output results required by the systolic array and generated by the input pattern generator, the processing element array makes a set of correlating comparisons, and outputs the results of the correlating comparisons to the boundary processing elements, so as to acquire the decoding results required by the CFRS decoding. The results indicate the frame boundary and scrambling code groups of the cell search in a wideband code division multiple access system.

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