Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2008-07-22
2008-07-22
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
Reexamination Certificate
active
07404113
ABSTRACT:
A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
REFERENCES:
patent: 4598388 (1986-07-01), Anderson
patent: 6154851 (2000-11-01), Sher et al.
patent: 6163489 (2000-12-01), Blodgett
patent: 6505314 (2003-01-01), Daehn
Fredeman Gregory J.
Hsu Louis L.
Joshi Rajiv V.
Kirihata Toshiaki
International Business Machines - Corporation
Lamarre Guy J
Verminski Brian P.
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