Piecewisely-controlled tri-state output buffer
Pin multiplexing
Pin programmable reference
Pin selection system for microcontroller having multiplexer sele
Pinout architecture for a family of multiple segmented programma
Pipe-lined static router and scheduler for configurable logic sy
Pipeline structure using positive edge and negative edge flip-fl
Pipeline-based circuit with a postponed clock-gating...
Pipelined clock distribution for self resetting CMOS circuits
Pipelined low-voltage current-mode logic with a switching...
PLA architecture having improved clock signal to output timing u
PLA late signal circuitry using a specialized gap cell and PLA l
PLA late signal circuitry using a specialized gap cell and PLA l
PLD configurable logic block enabling the rapid calculation...
PLD having a window pane architecture with segmented and stagger
PLD having a window pane architecture with segmented...
PLD lookup table including transistors of more than one...
PLD lookup table including transistors of more than one...
PLD memory cells utilizing metal-to-metal capacitors to...
PLD with selective inputs from local and global conductors