Pipelined clock distribution for self resetting CMOS circuits

Details Pipelined clock distribution for self resetting CMOS circuits Pipelined clock distribution for self resetting CMOS circuits

1996-06-10

1998-06-09

Allen, Stephone

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 17, H03K 1900

Patent

active

057640831

ABSTRACT:
A system for clocking self resetting CMOS (SRCMOS) circuits operating at high speed includes a clock generator circuit which produces a first pipeline clock pulse of relatively narrow width from a leading edge of a system clock having a relatively long duration with respect to the first pipeline clock, a number of delay circuits, the time duration of each of the delay circuits being determined by characteristics of evaluation logic in the SRCMOS circuits being clocked, the delay circuits being connected in a serial pipeline fashion such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration. The clocking system also includes a cycle relax mode whereby the clock pulse output of the clock generator circuit may be extended for test or diagnostic purposes.

REFERENCES:
patent: 3829790 (1974-08-01), Macrander
patent: 4414637 (1983-11-01), Stanley
patent: 4862096 (1989-08-01), Spence
patent: 5173618 (1992-12-01), Eisenstadt
patent: 5208776 (1993-05-01), Nasu et al.
patent: 5216301 (1993-06-01), Gleeson, III et al.
patent: 5258660 (1993-11-01), Nelson et al.
patent: 5389831 (1995-02-01), Eisenstadt
patent: 5517136 (1996-05-01), Harris et al.
patent: 5532625 (1996-07-01), Rajivan
patent: 5614845 (1997-03-01), Masleid
patent: 5638008 (1997-06-01), Rangasayee et al.

Affiliated with

Also associated with

Rating

Pipelined clock distribution for self resetting CMOS circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined clock distribution for self resetting CMOS circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined clock distribution for self resetting CMOS circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2204666