Pipeline-based circuit with a postponed clock-gating...

Details Pipeline-based circuit with a postponed clock-gating... Pipeline-based circuit with a postponed clock-gating...

2005-06-14

2005-06-14

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S086000, C713S322000, C713S600000, C327S141000

Reexamination Certificate

active

06906554

ABSTRACT:
A pipeline-based circuit with a postponed clock-gating mechanism and related driving method are disclosed for reducing power consumption, and the driving method does not deteriorate processing performance of the pipeline-based circuit. A pipeline-based circuit has a plurality of logic operators cascaded to form at least a pipeline, a pipeline control unit for generating at least a control signal to each logic operator for controlling whether one logic operator needs to pipe data to next logic operator, and a control value calculator for setting a valid bit of each logic operator following a currently activated logic operator according to the control signals generated from the pipeline control unit. When each logic operator begins operating, the related control value is used to determine whether or not a clock signal piping data of the present logic operator to next logic operator is gated to reduce power consumption. This postponed clock-gating mechanism avoids the degradation of pipeline clock speed limitation.

REFERENCES:
patent: 5918042 (1999-06-01), Furber
patent: 6204695 (2001-03-01), Alfke et al.
patent: 6594815 (2003-07-01), Lee et al.
patent: 6609209 (2003-08-01), Tiwari et al.
patent: 2004/0130927 (2004-07-01), Schulz et al.
patent: 2004/0170070 (2004-09-01), Rapp et al.

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