PLA architecture having improved clock signal to output timing u

Details PLA architecture having improved clock signal to output timing u PLA architecture having improved clock signal to output timing u

1995-12-27

1998-01-27

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, 326 93, H03K 19177

Patent

active

057125783

ABSTRACT:
A programmable logic array architecture having improved clock signal to output timing includes a logical AND plane and a logical OR plane. The logical AND plane generates a plurality of intermediary outputs responsive to the plurality of inputs. The logical OR plane then generates a plurality of outputs responsive to the plurality of intermediary outputs. The logical AND plane includes a plurality of semiconductors interconnected in a Type I dynamic logic configuration, and the logical OR plane includes a second plurality of semiconductors interconnected in a Type II dynamic logic configuration.

REFERENCES:
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 4950928 (1990-08-01), Schnizlein
patent: 4962327 (1990-10-01), Iwazaki
patent: 5010258 (1991-04-01), Usami et al.
patent: 5258666 (1993-11-01), Furuki
Popescu, Val, Merle Schultz, John Sprackle, Gary Gibson, Bruce Lightner and David Isaman, "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. 10-13 and 63-73.

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