PLD lookup table including transistors of more than one...

Details PLD lookup table including transistors of more than one... PLD lookup table including transistors of more than one...

2003-01-30

2004-07-27

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000, C326S113000, C327S407000, C327S408000

Reexamination Certificate

active

06768338

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to programmable logic devices (PLDs). More particularly, the invention relates to a lookup table for a PLD that includes transistors having more than one oxide thickness.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBS) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure.
More advanced FPGAs can include more than one type of logic block in the array. For example, the Xilinx Virtex-II Pro™ FPGA includes blocks of Random Access Memory (RAM), blocks implementing multiplier functions, and embedded processor blocks. (The Xilinx Virtex-II Pro FPGA is described in detail in pages 19-71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.)
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FPGA CLBS typically include several “lookup tables” (LUTs). A LUT is an addressable memory array that is typically loaded with data during the configuration process. For example, a Virtex-II Pro CLB includes eight LUTS. Each LUT has four data input terminals that address the configurable memory. By storing predetermined values in the appropriate memory locations, the LUT can be configured to provide any function of up to four variables.
FIG. 1
shows a typical LUT structure
100
, which includes 16 memory locations (configuration memory cells M
0
-M
15
) addressed by four input signals IN
0
-IN
3
. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The output of each memory cell passes through two pass transistors, one of transistors T
0
-T
15
followed by one of transistors U
0
-U
7
. Transistors T
0
-T
15
are controlled by LUT input signal IN
0
and its inverse (provided by inverter I
0
), while transistors U
0
-U
7
are controlled by LUT input signal IN
1
and its inverse (provided by inverter I
1
). After passing through these two transistors, the signals from the memory cells have been narrowed down to four signals on internal nodes INT
8
-INT
11
.
Each internal node INT
8
-INT
11
drives a corresponding buffer
101
a
-
101
d
. The output signals from buffers
101
a
-
101
d are again passed through two transistors, one of transistors V
0
-V
3
followed by one of transistors W
0
-W
1
. Transistors V
0
-V
3
are controlled by LUT input signal IN
2
and its inverse (provided by inverter I
2
), while transistors W
0
-W
1
are controlled by LUT input signal IN
3
and its inverse (provided by inverter I
3
). The one remaining signal (on internal node INT
14
) is passed through another buffer
102
to provide the LUT output signal OUT. Thus, by controlling the four pass transistors on each path between the memory cells and the LUT, and by configuring the memory cells to store the desired values, any function of up to four variables can be implemented.
FIG. 1A
shows a simplified configuration memory cell Mx that can be used to implement memory cells M
0
-M
15
of FIG.
1
. Configuration memory cell Mx can include, for example, a pair of cross-coupled inverters A, B, with two pass transistors d
1
, d
2
that allow the configuration logic (not shown) to access the memory cell. Configuration memory cells are well known in the art of FPGA design, therefore, detailed exemplary descriptions are not included herein.
FIG. 1B
illustrates one well-known implementation
101
x
of buffer
101
. Buffer
101
x
includes two inverters coupled in series. The first inverter includes P-channel transistor P
1
(the pullup) and N-channel transistor N
1
(the pulldown), coupled in series between power high VDD and ground GND. Optional second inverter I
4
can increase the performance of the buffer and ensures that the buffer output signal has the same sense as the buffer input signal. P-channel transistor P
2
is driven by the node N between the two inverters, and acts to pull node INT up to VDD such that pullup P
1
is fully turned off. Optional P-channel transistor P
3
is used to initialize node INT to a high value, for example during reset or power-up of the FPGA. Buffer
102
can be the same as buffer
10
x
, can omit the initialization pullup, or can be a simple inverter or some other well-known buffer circuit.
The structure shown in
FIG. 1
works well at sufficiently high values of VDD (power high, or the operating voltage of the FPGA). For example, for many years VDD was standardized at 5 volts (5 V), plus or minus ten percent (10%). (The ten percent allowable variation was included in the specifications of each device to allow for normal deviations in manufacturing and operation.) However, operating voltages are being steadily reduced both to save power and to meet the requirements of smaller and smaller transistors. For example, a transistor with a thinner oxide layer breaks down at a lower gate voltage than a transistor with a thicker oxide layer. Thus, values of VDD have been reduced to 2.5 V, then 1.8 V, and even as low as 1.5 V. A VDD value of 1.2 V is now contemplated, and at these low voltage levels the structure of
FIG. 1
is no longer adequate, as is now described in conjunction with FIG.
2
.
When a high value is passed through an N-channel transistor, the voltage is reduced by Vt, the threshold voltage level of the N-channel transistor. (For purposes of simplifying the present discussion, other well-known transistor effects such as the body effect are not described.) For example,
FIG. 2
shows an input signal IN passing through transistor T (which is driven by VDD) to internal node INT. Internal node INT drives buffer
201
, which provides the output signal OUT. When input signal IN is at the same voltage level as VDD, the voltage at internal node INT is the gate voltage reduced by one threshold voltage (VINT=VDD−Vt).
This well-known limitation presents no problem when VDD=5 V, as described above. When processes supporting this operating voltage are used, the N-channel threshold voltage is less than one volt (1 V). Thus, the voltage at internal node INT is still more than four volts (4 V), which is quite sufficient to turn on the N-channel pulldown N
1
, thus turning on P-channel pullup P
2
in buffer
201
(see FIG.
1
B). However, at sufficiently low levels of VDD, the voltage at internal node INT is so low as to impair the performance of the circuit.
For example, if node INT does not rise sufficiently high, the N-channel pulldown in buffer
201
might not be completely on, and the P-channel pullup P
2
might not be sufficiently on to quickly turn off pullup P
1
. Thus, the pullup (e.g., pullup P
1
) “fights” the pulldown (e.g., pulldown N
1
), and slows down the switching of the output node. For example, referring again to
FIG. 1B
, while P-channel transistor P
2
helps in raising node INT to VDD once node N goes low, transistor P
2
is no help if node N does not go low enough to turn it on.
As described, there is a voltage drop when a high voltage is passed across an N-channel transistor. However, there is no corresponding voltage drop of a high voltage across a P-channel transistor. Therefore, one solution to this problem is to replace the N-channel transistor with paired N- and P-channel transistors, with the P-channel transistors being driven by the complementary input signal. However, th

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