Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-05-19
2001-06-05
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
06242947
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to programmable logic devices (PLDs) and more particularly to improved routing in PLDs having subarrays of configurable logic block tiles.
2. Related Art
Field programmable gate arrays (FPGAs) are well known in the art of PLDs. An FPGA typically includes an array of configurable logic blocks (CLBs) that are programmably interconnected to each other to provide logic functions desired by a user. The architecture of some FPGAs may be described as including “tiles”, wherein each tile includes a CLB as well as a portion of an interconnect structure. “The 1998 Programmable Logic Data Book”, pages 4-225 to 4-241, published by Xilinx, Inc. of San Jose, California, describes such a tile architecture as provided in the XC5200™ FPGA family, and is incorporated by reference herein.
To increase the complexity and size of the logic functions provided by an FPGA, the number of CLBs can be increased. However, this increase in CLBs then requires proportionately more interconnect structure. A common way of providing more interconnect structure is to add more wiring. Unfortunately, adding wiring significantly decreases silicon efficiency because each tile must provide worst case (i.e. maximum) interconnect resources, thereby making each tile larger and more complex. This increase in size and complexity at the tile level in turn increases the size, complexity, and ultimately cost of the FPGA.
One way of overcoming these disadvantages is to divide the tiles of the FPGA into a plurality of arrays (also called subarrays herein) and provide added routing channels between the arrays to interconnect the arrays. An FPGA architecture having a plurality of arrays of tiles is referred to herein as a window pane architecture because it resembles a large glass window divided into a plurality of smaller window panes. U.S. Pat. No. 5,455,525, issued to Ho et al. on Oct. 3, 1995, discloses such an architecture. In addition, Lucent sells an Optimized Reconfigurable Cell Array (ORCA) FPGA which has a window pane architecture.
FIG. 1
illustrates an FPGA
10
having a window pane architecture including four arrays
12
. In this embodiment, each array
12
includes a 7×7 array of tiles
15
. Vertical and horizontal routing channels
14
are provided between arrays
12
. The wiring in routing channels
14
, which extends the full length of the FPGA, provides hierarchical routing in FPGA
10
. Specifically, the wiring included in routing channels
14
(also called long lines) is coupled to other interconnect and CLBs (neither shown) in tiles
15
located adjacent routing channels
14
. Therefore, such long lines can become heavily loaded with multiple potential connections to numerous tiles and thus become incapable of driving all connections to proper levels without buffers. Furthermore, such long lines are inherently highly capacitive and thus slow, thereby causing timing problems which can be critical to overall FPGA performance.
Therefore, a need arises for a window pane architecture which overcomes the noted deficiencies of the prior art.
SUMMARY OF THE INVENTION
The present invention is incorporated into a programmable logic device having a window pane configuration, i.e. a large number of configurable logic block tiles divided into a plurality of arrays with routing channels between the arrays. In accordance with the present invention, segmenting and staggering routing wires in these routing channels significantly reduces excess loading and the need for buffers compared to prior art longline resources. Specifically, segmenting and staggering of the routing wires ensure effective connectivity in the programmable logic device, while substantially eliminating the longline capacitive-induced time delay of the prior art. Thus, the present invention allows use of window pane architectures for large arrays and provides significant advantages over the prior art.
In one embodiment of the present invention, each routing wire occupies a track in the routing channel and is coupled to respective configurable logic block tiles in each adjacent array identically. In other embodiments, at least one routing wire occupies a plurality of tracks in the routing channel but is still coupled to respective configurable logic block tiles in each adjacent array identically.
Various connection-related improvements may also be made in the present invention. In one such improvement, a switch matrix normally used within each tile for internal routing is also used in the routing channel to selectively route signals between the routing wires and the configurable logic block tiles. Programmable interconnect points are employed in another such improvement to facilitate interconnection between the routing wires in the channel and selected configurable logic block tiles.
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patent: 5455525 (1995-10-01), Ho et al.
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“The Programmable Logic Data Book”, copyright 1998, available from Xilinx, Inc. at 2100 Logic Drive, San Jose, California 95124, pp. 4-225 to 4-241.
“More FPGAS” by W. R. Moore & W. Luk (eds.), Article by Malkit S. Jhitta, “Introduction of a New FPGA Architecture”, 1994, published by Abingdon EE&CS Books, 49 Five Mile Drive, Oxford OX2 8HR, United Kingdom, pp. 13-23.
Cartier Lois D.
Harms Jeanette S.
Le Don Phu
Tokar Michael
Xilinx , Inc.
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