Piecewisely-controlled tri-state output buffer

Details Piecewisely-controlled tri-state output buffer Piecewisely-controlled tri-state output buffer

1993-10-28

1996-01-02

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 27, 326 58, H03K 1902

Patent

active

054812089

ABSTRACT:
A piecewisely-controlled tri-state output buffer has a signal buffer portion, an output falling-edge detector capable of generating a falling-edge control signal, an output rising-edge detector capable of generating a rising-edge control signal, and a signal output portion. The signal output portion includes one pair of PMOS transistors connected in parallel and one pair of NMOS transistors connected in parallel. One of the pair of PMOS transistors has a structural width larger than that of another PMOS transistor, and one of the pair of NMOS transistors has a structural width larger than that of another NMOS transistor. The gate of the one PMOS transistor is controlled by the rising-edge control signal while the gate of the one NMOS transistor is controlled by the falling-edge control signal.

REFERENCES:
patent: 4731553 (1988-03-01), Van Lehn
patent: 5121013 (1992-06-01), Chuang
patent: 5122690 (1992-06-01), Bianchi
patent: 5306965 (1994-04-01), Asprey
patent: 5332932 (1994-07-01), Runaldue

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