PLD having a window pane architecture with segmented and stagger

Electronic digital logic circuitry – Multifunctional or programmable – Array

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326 39, H03K 19177

Patent

active

060844299

ABSTRACT:
A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks, interconnect, and routing wires may be accomplished with switch matrices and programmable interconnect points.

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"More FPGAS" by W. R. Moore & Luk (eds.), Article by Malkit S. Jhitta, "Introduction of a New FPGA Architecture", 1994, published by Abingdon EE&CS Books, 49 Five Mile Drive, Oxford OX2 8HR, UK, pp 13-23.

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