Pipeline structure using positive edge and negative edge flip-fl

Details Pipeline structure using positive edge and negative edge flip-fl Pipeline structure using positive edge and negative edge flip-fl

1995-10-25

1997-07-08

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 46, 327201, H03K 190175

Patent

active

056465556

ABSTRACT:
To obtain a semiconductor integrated circuit reduced in hardware size, by avoiding duplication of a common constitution. A logic block (100) comprises logic means (A), logic means (B), and logic means (C), and the output of a pipeline register (11) is connected to the logic means (A) through a signal line (a), and the logic means (A) and logic means (B) are connected through a signal line (b). The logic means (A) is also connected to the logic means (C) through a signal line (c), and the logic means (C) is connected to the input of a pipeline register (21) through a signal line (d). When performing the same logic action in the first half period and second half period of a clock signal, it is not necessary to install two identical logic means, so that the size of the hardware may be reduced as compared with the constitution of installing two identical logic means.

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