Electronic digital logic circuitry – Reliability
Reexamination Certificate
2006-06-20
2006-06-20
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Reliability
C326S015000, C326S047000, C326S101000
Reexamination Certificate
active
07064574
ABSTRACT:
Structures and methods of reducing the susceptibility of programmable logic device (PLD) configuration memory cells to single event upsets (SEUs) by selectively adding metal-to-metal capacitors thereto. By adding capacitance to storage nodes in a memory cell, the susceptibility of the memory cell to SEUs is reduced. However, the performance of the memory cell also suffers. In PLD configuration memory cells, performance is not the most important factor. Therefore, for example, SEU-reducing capacitors can be selectively added to the PLD configuration memory cells while omitting the capacitors from user storage elements (e.g., block RAM) within the PLD. Thus, performance of the user storage elements is not adversely affected. Further, the use of metal-to-metal capacitors is well-suited to the configuration memory cells of a PLD, because these memory cells typically have additional area available for the capacitors above the programmable logic elements controlled by the associated configuration memory cells.
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Voogel Martin L.
Young Steven P.
Cartier Lois D.
Tran Anh Q.
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