Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2002-08-30
2004-12-21
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S047000
Reexamination Certificate
active
06833730
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to Programmable Logic Devices (PLDs). More particularly, the invention relates to a configurable logic block (CLB) for a PLD that enables the rapid calculation of sum-of-products (SOP) functions.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The CLBS, IOBS, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBS, IOBS, and interconnect structure are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as ASIC devices (Application Specific Integrated Circuits). PLDS can also be implemented in other ways, e.g., using fuse or antifuse technology.
One type of PLD is the Virtex™-II family of FPGAs from Xilinx, Inc. (The Virtex-II FPGA is described in detail in pages 33-75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.) A Virtex-II FPGA includes an array of configurable logic blocks (CLBs) as described above.
FIG. 1
is a simplified diagram of a Virtex-II CLB.
As shown in
FIG. 1
, a Virtex-II CLB includes four similar slices, SLICEs
0
through SLICE
3
. Each slice includes two lookup tables (LUT
1
, LUT
2
). Each LUT has an associated carry multiplexer (CY
1
, CY
2
), two associated multiplexers (M
1
and MX
1
, M
2
and MX
2
), and an associated flip-flop (FF
1
, FF
2
). By programming the various multiplexers, each LUT output can be provided as a slice output signal and/or can be registered in the associated flip-flop. Each LUT output can also be placed on the carry chain or can alter a value already present on the carry chain. These aspects of CLBs are well known, and therefore are not described further herein.
However, each Virtex-II slice also includes an “SOP chain”, or sum-of-products chain. The SOP chain includes a multiplexer ORM that selects between an OR-input signal (e.g., OIN
0
) and a logic low level (“0”) under the control of a configuration memory cell (not shown). The output of multiplexer ORM is ORed together with the carry chain output COUT for the slice in OR gate “OR”. The output of OR gate “OR” is passed along the SOP chain to multiplexer ORM in the adjacent slice.
Note that in the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals. Further, in CMOS logic an OR gate is typically implemented as a NAND-gate with inverted input signals. However, in the present specification the “OR” symbol is used to simplify the drawings and to accurately represent the logical function. The term “OR gate” is also used herein to represent logic implementing the OR function, however implemented.
The SOP chain of
FIG. 1
can be used to implement sum-of-products functions, as shown in FIG.
1
A. For example, to implement a sum-of-products function each LUT (LUT
1
, LUT
2
in each slice) is programmed to implement an AND function. The carry chain (CY
1
, CY
2
in each slice) is then used to combine the AND functions into wider AND functions, as shown in FIG.
1
A. The OR gates in the SOP chain (gate “OR” in each slice) are then combined to provide the sum-of-products output signal, AND
16
OR
2
. Thus, as shown in
FIG. 1A
, a single Virtex-II CLB can be used to implement a 2-input OR function of two 16-input AND functions (i.e., the sum-of-products function of two product terms, each with 16 inputs). Additional inputs can be added to each AND function (i.e., to each product term) by extending the carry chains into vertically adjacent CLBs. Additional inputs can be added to each OR function by extending the SOP chain into horizontally adjacent CLBs.
While the CLB architecture of
FIG. 1
enables the efficient implementation of sum-of-products functions, the speed of the computation is limited by the speed of the carry chain. In particular, getting “onto” and “off of” a carry chain typically carries a significant delay penalty. Alireza S. Kaviani proposes an alternative CLB architecture that bypasses the carry chain in commonly assigned, co-pending U.S. patent application Ser. No. 09/687,812, entitled “Configurable Logic Block for PLD” and filed Oct. 13, 2000, which is hereby incorporated herein by reference. This alternative architecture is illustrated in FIG.
2
.
The CLB of
FIG. 2
includes four similar slices, each slice (SLICE
0
through SLICE
3
) being similar to those shown in FIG.
1
. However, in the architecture of
FIG. 2
, each slice includes an additional function generator FG. Function generator FG can be configured (e.g., by bits stored in configuration memory cells, not shown) to implement either a 2-input NOR function of the two LUT output signals, a 2-input NAND function of the two LUT output signals, a constant high value generator, or to pass another value supplied from elsewhere inside the CLB. To implement a sum-of-products function, function generator FG is configured to function as a 2-input NOR gate.
As shown in
FIG. 2A
, each LUT in slices SLICE
1
and SLICE
3
is configured as a NAND gate. The function generator FG of each slice is configured as a 2-input NOR gate. As is well known in the art of logic design, two NAND gates followed by a NOR gate are logically equivalent to a single wide AND gate. Therefore, the output of each function generator FG is the AND function of all eight LUT inputs for that slice, i.e., an 8-input product term. The product terms are then combined together in the SOP chain as in the CLB architecture of FIG.
1
.
This architecture avoids the delay of the carry chain. Instead, the delay from a LUT output to the SOP chain (i.e., to an input terminal of one of the OR gates in the chain) is only the delay through function generator FG. However, the architecture of
FIG. 2
also has its limitations. For example, the removal of the carry chain has resulted in a maximum of 8 AND inputs, rather than the virtually unlimited number of inputs supported in FIG.
1
. Further, the delay from a LUT input terminal to the AND
8
OR
2
output terminal includes not only the delay through the FG function generator, but an additional delay of up to two OR gate delays.
Therefore, Kaviani further proposes a second alternative CLB architecture, which is also disclosed in commonly assigned, co-pending U.S. patent application Ser. No. 09/687,812. In the architecture of
FIG. 3
, each slice includes the function generator FG as in FIG.
2
. However, the SOP chain is omitted. Instead, the CLB includes a dedicated 4-input OR gate
301
that performs a logical OR function of the four output signals (OUT
0
-OUT
3
) from the four function generators FG of the four slices in the CLB. (The term “dedicated” is used herein to describe a circuit designed to perform a single function, e.g., an OR function, as opposed to a circuit that can be programmed to implement any of a variety of functions. For example, OR gate
301
is a dedicated circuit, while function generator FG is not.)
Using the architecture of
FIG. 3
, a sum-of-products function can be implemented as shown in FIG.
3
A. Each LUT is configured as a NAND gate, as in the architecture
Ganesan Satish R.
Kasat Amit
Cartier Lois D.
Tan Vibol
Xilinx , Inc.
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